159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
/**
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Header file for CC (Core Communicator) module.
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This file is the header file that define the API and data type
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for CC module.
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@file CC.h
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@ingroup mIDrvSys_CC
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2011. All rights reserved.
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*/
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#ifndef _CC_H
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#define _CC_H
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#if defined(__UITRON)
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#include "Type.h"
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#else
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#include "nvt_type.h"
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#endif
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/**
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@addtogroup mIDrvSys_CC
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*/
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//@{
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typedef enum {
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CC_CORE_MIPS1 = 0x0, ///< 1st Core MIPS1
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CC_CORE_MIPS2, ///< 2nd Core MIPS2
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CC_CORE_DSP, ///< 3rd Core DSP
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CC_CORE_NUM,
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ENUM_DUMMY4WORD(CC_CORE_ID)
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} CC_CORE_ID;
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typedef enum {
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CC_EVT_FROM_CPU1 = 0x00000001,
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CC_EVT_FROM_CPU2 = 0x00000002,
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CC_EVT_FROM_DSP = 0x00000004,
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CC_ACK_FROM_CPU1 = 0x00000008,
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CC_ACK_FROM_CPU2 = 0x00000010,
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CC_ACK_FROM_DSP = 0x00000020,
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CC_CPU2_GOES_SLEEP = 0x00000040,
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// CC_DSP_GOES_LIGHT_SLEEP = 0x00000080,
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// CC_DSP_GOES_STANDBY = 0x00000100,
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CC_EVT_ERR = 0xFFFFFFFF,
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ENUM_DUMMY4WORD(CC_EVENT)
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} CC_EVENT;
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typedef enum {
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CC_CORE_REQ_1 = 0x0,
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CC_CORE_REQ_2,
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CC_CORE_REQ_3,
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CC_CORE_REQ_4,
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CC_CORE_REQ_MAX,
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ENUM_DUMMY4WORD(CC_CORE_REQ_NUM)
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} CC_CORE_REQ_NUM;
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typedef enum {
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CC_CONFIG_ID_MIPS2_BASE_ADDRESS = 1, ///< Configured CPU exception base address
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///< @note represent code start point running @ MIPS2
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///< Context is :
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///< - @b UINT32 : address of base address
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CC_CONFIG_ID_CTRL_SRST, ///< CC controller will reset to default value except MIPS2 & DSP base address
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///< - @b NULL
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CC_CONFIG_ID_SET_MIPS1_REQ, ///< Set MIPS1 request slot number of each process cycle
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///< Context is :
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///< - @b CC_CORE_REQ_NUM : slot number of each process cycle(1-4)
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CC_CONFIG_ID_SET_MIPS2_REQ, ///< Set MIPS2 request slot number of each process cycle
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///< Context is :
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///< - @b CC_CORE_REQ_NUM : slot number of each process cycle(1-4)
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CC_CONFIG_ID_SET_DSP_EPP_REQ, ///< Set DSP EPP request slot number of each process cycle
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///< Context is :
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///< - @b CC_CORE_REQ_NUM : slot number of each process cycle(1-4)
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CC_CONFIG_ID_SET_DSP_EDP_REQ, ///< Set DSP EDP request slot number of each process cycle
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///< Context is :
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///< - @b CC_CORE_REQ_NUM : slot number of each process cycle(1-4)
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CC_CONFIG_ID_SET_DSP_PINT_BASE_ADDRESS, ///< Set DSP Program_Int source data base address
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///< Context is :
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///< - @b UINT32 : address of base address
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CC_CONFIG_ID_SET_DSP_ISDM_BASE_ADDRESS, ///< Set DSP Scaler memory source data base address
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///< Context is :
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///< - @b UINT32 : address of base address
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CC_CONFIG_ID_SET_DSP_IVDM_BASE_ADDRESS, ///< Set DSP Vector memory source data base address
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///< Context is :
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///< - @b UINT32 : address of base address
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CC_CONFIG_ID_CPU2_SLEEP_INT, ///< Set CC CPU2 sleep interrupt enable or disable
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///< Context is :
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///< - @b BOOL : enable or disable
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ENUM_DUMMY4WORD(CC_CONFIG_ID)
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} CC_CONFIG_ID;
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// Core Communicator handler
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typedef void (*CC_HANDLER)(UINT32 uiEvent);
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typedef struct {
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UINT32 uiCMDID; ///< Command ID, a serial number from 1 to 0xFFFF
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///< @note For cc_getCoreXCMD() only, generated by CC driver.
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UINT32 uiCMDOperation; ///< Command operation, from 0 to 0xFFFF
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UINT32 *pData; ///< Command data
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///< @note Not the address of data that will be processed by this command
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UINT32 uiDataSize; ///< Command data size in bytes
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///< @note Not the size of data that will be processed by this command
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} CC_CMD, *PCC_CMD;
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extern ER cc_open(void);
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extern ER cc_close(void);
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extern void cc_registerCore2Handler(CC_HANDLER Hdl);
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extern void cc_registerCore3Handler(CC_HANDLER Hdl);
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extern ER cc_sendCore2CMD(PCC_CMD pCMD);
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extern ER cc_sendCore3CMD(PCC_CMD pCMD);
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extern void cc_getCore2CMD(PCC_CMD pCMD);
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extern void cc_getCore3CMD(PCC_CMD pCMD);
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extern void cc_ackCore2CMD(void);
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extern void cc_ackCore3CMD(void);
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extern void cc_setCore2Base(UINT32 uiBaseAddr);
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//extern void cc_setCore3BootVector(UINT32 uiBVAddr);
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extern UINT32 cc_getCore2Base(void);
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//extern UINT32 cc_getCore3BootVector(void);
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extern void cc_stopCore(CC_CORE_ID uiCoreID);
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extern ER cc_startCore(CC_CORE_ID uiCoreID);
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extern void cc_setConfig(CC_CONFIG_ID ConfigID, UINT32 uiConfig);
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extern INT32 cc_getHwResGrant(CC_CORE_ID uiCoreID);
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extern INT32 cc_getHwResReqFlag(CC_CORE_ID uiCoreID);
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extern CC_EVENT cc_waitCoreEntrySleep(CC_EVENT uiEvt);
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extern void cc_configCoreOutstanging(CC_CORE_ID uiCoreID, BOOL bArbEn, BOOL bApbEn);
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//@}
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#endif
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