109 lines
6.4 KiB
C
Executable File
109 lines
6.4 KiB
C
Executable File
#ifndef _NA51089_HASH_H_
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#define _NA51089_HASH_H_
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typedef enum {
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NA51089_HASH_MCLK_240MHZ = 0,
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NA51089_HASH_MCLK_320MHZ,
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NA51089_HASH_MCLK_RSVD,
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NA51089_HASH_MCLK_PLL9,
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NA51089_HASH_MCLK_MAX
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} NA51089_HASH_MCLK_T;
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typedef enum {
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NA51089_HASH_MODE_SHA1 = 0, ///< block size=> 64 bytes, digest size 20 bytes
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NA51089_HASH_MODE_SHA256, ///< block size=> 64 bytes, digest size 32 bytes
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NA51089_HASH_MODE_HMAC_SHA1, ///< block size=> 64 bytes, digest size 20 bytes
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NA51089_HASH_MODE_HMAC_SHA256, ///< block size=> 64 bytes, digest size 32 bytes
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NA51089_HASH_MODE_MAX
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} NA51089_HASH_MODE_T;
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typedef enum {
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NA51089_HASH_IV_SEL_DEFAULT = 0, ///< HASH IV from algorithm default
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NA51089_HASH_IV_SEL_REGISTER, ///< HASH IV from register HASH_IV_0 to HASH_IV_7
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NA51089_HASH_IV_MAX
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} NA51089_HASH_IV_SEL_T;
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typedef enum {
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NA51089_HASH_ACCMODE_PIO = 0, ///< HASH access mode PIO
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NA51089_HASH_ACCMODE_DMA, ///< HASH access mode DMA
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NA51089_HASH_ACCMODE_MAX
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} NA51089_HASH_ACCMODE_T;
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typedef enum {
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NA51089_HASH_DMA_PAD_DISABLE = 0, ///< HASH padding disable, DMA mode only
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NA51089_HASH_DMA_PAD_ENABLE, ///< HASH padding enable, DMA mode only
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NA51089_HASH_DMA_PAD_MAX
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} NA51089_HASH_DMA_PAD_T;
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typedef enum {
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NA51089_HASH_BYPASS_NORMAL = 0, ///< HASH engine as normal mode
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NA51089_HASH_BYPASS_HWCOPY, ///< HASH engine as HwCopy
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NA51089_HASH_BYPASS_MAX
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} NA51089_HASH_BYPASS_T;
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typedef enum {
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NA51089_HASH_INIT_DISABLE = 0, ///< Set engine as normal state, PIO mode only
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NA51089_HASH_INIT_ENABLE, ///< Set engine as initail state, PIO mode only
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NA51089_HASH_INIT_MAX
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} NA51089_HASH_INIT_T;
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typedef enum {
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NA51089_HASH_IPAD_DISABLE = 0, ///< Set HASH engine as normal state
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NA51089_HASH_IPAD_ENABLE, ///< Set HASH engine as internal padding state
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NA51089_HASH_IPAD_MAX
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} NA51089_HASH_IPAD_T;
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typedef enum {
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NA51089_HASH_OPAD_DISABLE = 0, ///< Set HASH engine as normal state
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NA51089_HASH_OPAD_ENABLE, ///< Set HASH engine as external padding state
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NA51089_HASH_OPAD_MAX
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} NA51089_HASH_OPAD_T;
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#define NA51089_HASH_MAX_IV_SIZE 32 ///< 32 Bytes, SHA1=> 20 bytes, SHA256=> 32 bytes
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#define NA51089_HASH_MAX_DIGEST_SIZE 32 ///< 32 Bytes, SHA1=> 20 bytes, SHA256=> 32 bytes
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#define NA51089_HASH_MAX_KEY_SIZE 64 ///< 64 Bytes
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#define NA51089_HASH_CFG_REG 0x00 ///< configuration
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#define NA51089_HASH_PADLEN_REG 0x04 ///< message length for DMA mode auto padding used
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#define NA51089_HASH_INT_ENB_REG 0x08 ///< interrupt enable
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#define NA51089_HASH_INT_STS_REG 0x0C ///< interrupt status
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#define NA51089_HASH_KEY0_REG 0x10 ///< key 0 ~ 31 bit
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#define NA51089_HASH_KEY1_REG 0x14 ///< key 32 ~ 63 bit
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#define NA51089_HASH_KEY2_REG 0x18 ///< key 64 ~ 95 bit
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#define NA51089_HASH_KEY3_REG 0x1C ///< key 96 ~ 127 bit
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#define NA51089_HASH_KEY4_REG 0x20 ///< key 128 ~ 159 bit
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#define NA51089_HASH_KEY5_REG 0x24 ///< key 160 ~ 191 bit
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#define NA51089_HASH_KEY6_REG 0x28 ///< key 192 ~ 223 bit
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#define NA51089_HASH_KEY7_REG 0x2C ///< key 224 ~ 255 bit
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#define NA51089_HASH_KEY8_REG 0x30 ///< key 256 ~ 287 bit
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#define NA51089_HASH_KEY9_REG 0x34 ///< key 288 ~ 319 bit
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#define NA51089_HASH_KEY10_REG 0x38 ///< key 320 ~ 351 bit
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#define NA51089_HASH_KEY11_REG 0x3C ///< key 352 ~ 383 bit
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#define NA51089_HASH_KEY12_REG 0x40 ///< key 384 ~ 415 bit
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#define NA51089_HASH_KEY13_REG 0x44 ///< key 416 ~ 447 bit
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#define NA51089_HASH_KEY14_REG 0x48 ///< key 448 ~ 479 bit
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#define NA51089_HASH_KEY15_REG 0x4C ///< key 480 ~ 511 bit
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#define NA51089_HASH_IV0_REG 0x50 ///< initial vector 0 ~ 31 bit
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#define NA51089_HASH_IV1_REG 0x54 ///< initial vector 32 ~ 63 bit
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#define NA51089_HASH_IV2_REG 0x58 ///< initial vector 64 ~ 95 bit
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#define NA51089_HASH_IV3_REG 0x5c ///< initial vector 96 ~ 127 bit
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#define NA51089_HASH_IV4_REG 0x60 ///< initial vector 128 ~ 159 bit
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#define NA51089_HASH_IV5_REG 0x64 ///< initial vector 160 ~ 191 bit
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#define NA51089_HASH_IV6_REG 0x68 ///< initial vector 192 ~ 223 bit
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#define NA51089_HASH_IV7_REG 0x6c ///< initial vector 224 ~ 255 bit
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#define NA51089_HASH_OUT0_REG 0x70 ///< output data 0 ~ 31 bit
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#define NA51089_HASH_OUT1_REG 0x74 ///< output data 32 ~ 63 bit
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#define NA51089_HASH_OUT2_REG 0x78 ///< output data 64 ~ 95 bit
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#define NA51089_HASH_OUT3_REG 0x7c ///< output data 96 ~ 127 bit
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#define NA51089_HASH_OUT4_REG 0x80 ///< output data 128 ~ 159 bit
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#define NA51089_HASH_OUT5_REG 0x84 ///< output data 160 ~ 191 bit
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#define NA51089_HASH_OUT6_REG 0x88 ///< output data 192 ~ 223 bit
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#define NA51089_HASH_OUT7_REG 0x8c ///< output data 224 ~ 255 bit
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#define NA51089_HASH_PIO_IN_REG 0x90 ///< input data 0 ~ 31 bit, PIO mode
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#define NA51089_HASH_DMA_SRC_REG 0x94 ///< source dma address, word alignment
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#define NA51089_HASH_DMA_DST_REG 0x98 ///< destination dma address, word alignment
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#define NA51089_HASH_DMA_TX_SIZE_REG 0x9c ///< hash message size, byte unit and alignment
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#define NA51089_HASH_KEY_READ_REG 0xA0 ///< hash key readable control
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#endif /* _NA51089_HASH_H_ */
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