1034 lines
25 KiB
C
1034 lines
25 KiB
C
/*
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* SMP support for power macintosh.
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*
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* We support both the old "powersurge" SMP architecture
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* and the current Core99 (G4 PowerMac) machines.
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*
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* Note that we don't support the very first rev. of
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* Apple/DayStar 2 CPUs board, the one with the funky
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* watchdog. Hopefully, none of these should be there except
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* maybe internally to Apple. I should probably still add some
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* code to detect this card though and disable SMP. --BenH.
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*
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* Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
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* and Ben Herrenschmidt <benh@kernel.crashing.org>.
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*
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* Support for DayStar quad CPU cards
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* Copyright (C) XLR8, Inc. 1994-2000
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/sched/hotplug.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/hardirq.h>
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#include <linux/cpu.h>
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#include <linux/compiler.h>
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#include <asm/ptrace.h>
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#include <linux/atomic.h>
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#include <asm/code-patching.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/time.h>
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#include <asm/mpic.h>
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#include <asm/cacheflush.h>
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#include <asm/keylargo.h>
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#include <asm/pmac_low_i2c.h>
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#include <asm/pmac_pfunc.h>
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#include "pmac.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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extern void __secondary_start_pmac_0(void);
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static void (*pmac_tb_freeze)(int freeze);
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static u64 timebase;
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static int tb_req;
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#ifdef CONFIG_PPC_PMAC32_PSURGE
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/*
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* Powersurge (old powermac SMP) support.
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*/
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/* Addresses for powersurge registers */
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#define HAMMERHEAD_BASE 0xf8000000
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#define HHEAD_CONFIG 0x90
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#define HHEAD_SEC_INTR 0xc0
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/* register for interrupting the primary processor on the powersurge */
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/* N.B. this is actually the ethernet ROM! */
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#define PSURGE_PRI_INTR 0xf3019000
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/* register for storing the start address for the secondary processor */
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/* N.B. this is the PCI config space address register for the 1st bridge */
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#define PSURGE_START 0xf2800000
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/* Daystar/XLR8 4-CPU card */
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#define PSURGE_QUAD_REG_ADDR 0xf8800000
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#define PSURGE_QUAD_IRQ_SET 0
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#define PSURGE_QUAD_IRQ_CLR 1
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#define PSURGE_QUAD_IRQ_PRIMARY 2
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#define PSURGE_QUAD_CKSTOP_CTL 3
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#define PSURGE_QUAD_PRIMARY_ARB 4
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#define PSURGE_QUAD_BOARD_ID 6
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#define PSURGE_QUAD_WHICH_CPU 7
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#define PSURGE_QUAD_CKSTOP_RDBK 8
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#define PSURGE_QUAD_RESET_CTL 11
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#define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
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#define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
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#define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
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#define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
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/* virtual addresses for the above */
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static volatile u8 __iomem *hhead_base;
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static volatile u8 __iomem *quad_base;
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static volatile u32 __iomem *psurge_pri_intr;
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static volatile u8 __iomem *psurge_sec_intr;
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static volatile u32 __iomem *psurge_start;
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/* values for psurge_type */
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#define PSURGE_NONE -1
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#define PSURGE_DUAL 0
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#define PSURGE_QUAD_OKEE 1
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#define PSURGE_QUAD_COTTON 2
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#define PSURGE_QUAD_ICEGRASS 3
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/* what sort of powersurge board we have */
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static int psurge_type = PSURGE_NONE;
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/* irq for secondary cpus to report */
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static struct irq_domain *psurge_host;
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int psurge_secondary_virq;
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/*
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* Set and clear IPIs for powersurge.
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*/
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static inline void psurge_set_ipi(int cpu)
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{
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if (psurge_type == PSURGE_NONE)
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return;
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if (cpu == 0)
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in_be32(psurge_pri_intr);
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else if (psurge_type == PSURGE_DUAL)
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out_8(psurge_sec_intr, 0);
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else
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
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}
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static inline void psurge_clr_ipi(int cpu)
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{
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if (cpu > 0) {
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switch(psurge_type) {
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case PSURGE_DUAL:
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out_8(psurge_sec_intr, ~0);
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case PSURGE_NONE:
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break;
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default:
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
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}
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}
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}
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/*
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* On powersurge (old SMP powermac architecture) we don't have
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* separate IPIs for separate messages like openpic does. Instead
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* use the generic demux helpers
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* -- paulus.
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*/
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static irqreturn_t psurge_ipi_intr(int irq, void *d)
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{
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psurge_clr_ipi(smp_processor_id());
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smp_ipi_demux();
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return IRQ_HANDLED;
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}
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static void smp_psurge_cause_ipi(int cpu)
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{
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psurge_set_ipi(cpu);
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}
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static int psurge_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq);
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return 0;
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}
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static const struct irq_domain_ops psurge_host_ops = {
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.map = psurge_host_map,
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};
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static int psurge_secondary_ipi_init(void)
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{
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int rc = -ENOMEM;
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psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL);
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if (psurge_host)
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psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
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if (psurge_secondary_virq)
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rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
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IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
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if (rc)
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pr_err("Failed to setup secondary cpu IPI\n");
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return rc;
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}
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/*
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* Determine a quad card presence. We read the board ID register, we
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* force the data bus to change to something else, and we read it again.
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* It it's stable, then the register probably exist (ugh !)
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*/
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static int __init psurge_quad_probe(void)
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{
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int type;
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unsigned int i;
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type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
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if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
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|| type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
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return PSURGE_DUAL;
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/* looks OK, try a slightly more rigorous test */
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/* bogus is not necessarily cacheline-aligned,
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though I don't suppose that really matters. -- paulus */
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for (i = 0; i < 100; i++) {
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volatile u32 bogus[8];
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bogus[(0+i)%8] = 0x00000000;
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bogus[(1+i)%8] = 0x55555555;
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bogus[(2+i)%8] = 0xFFFFFFFF;
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bogus[(3+i)%8] = 0xAAAAAAAA;
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bogus[(4+i)%8] = 0x33333333;
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bogus[(5+i)%8] = 0xCCCCCCCC;
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bogus[(6+i)%8] = 0xCCCCCCCC;
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bogus[(7+i)%8] = 0x33333333;
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wmb();
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asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
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mb();
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if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
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return PSURGE_DUAL;
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}
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return type;
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}
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static void __init psurge_quad_init(void)
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{
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int procbits;
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if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
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procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
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if (psurge_type == PSURGE_QUAD_ICEGRASS)
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PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
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else
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PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
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mdelay(33);
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out_8(psurge_sec_intr, ~0);
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PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
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PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
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if (psurge_type != PSURGE_QUAD_ICEGRASS)
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PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
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PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
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mdelay(33);
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PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
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mdelay(33);
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PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
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mdelay(33);
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}
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static void __init smp_psurge_probe(void)
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{
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int i, ncpus;
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struct device_node *dn;
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/* We don't do SMP on the PPC601 -- paulus */
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if (PVR_VER(mfspr(SPRN_PVR)) == 1)
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return;
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/*
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* The powersurge cpu board can be used in the generation
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* of powermacs that have a socket for an upgradeable cpu card,
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* including the 7500, 8500, 9500, 9600.
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* The device tree doesn't tell you if you have 2 cpus because
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* OF doesn't know anything about the 2nd processor.
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* Instead we look for magic bits in magic registers,
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* in the hammerhead memory controller in the case of the
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* dual-cpu powersurge board. -- paulus.
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*/
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dn = of_find_node_by_name(NULL, "hammerhead");
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if (dn == NULL)
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return;
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of_node_put(dn);
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hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
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quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
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psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
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psurge_type = psurge_quad_probe();
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if (psurge_type != PSURGE_DUAL) {
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psurge_quad_init();
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/* All released cards using this HW design have 4 CPUs */
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ncpus = 4;
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/* No sure how timebase sync works on those, let's use SW */
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smp_ops->give_timebase = smp_generic_give_timebase;
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smp_ops->take_timebase = smp_generic_take_timebase;
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} else {
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iounmap(quad_base);
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if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
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/* not a dual-cpu card */
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iounmap(hhead_base);
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psurge_type = PSURGE_NONE;
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return;
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}
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ncpus = 2;
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}
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if (psurge_secondary_ipi_init())
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return;
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psurge_start = ioremap(PSURGE_START, 4);
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psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
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/* This is necessary because OF doesn't know about the
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* secondary cpu(s), and thus there aren't nodes in the
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* device tree for them, and smp_setup_cpu_maps hasn't
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* set their bits in cpu_present_mask.
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*/
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if (ncpus > NR_CPUS)
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ncpus = NR_CPUS;
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for (i = 1; i < ncpus ; ++i)
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set_cpu_present(i, true);
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if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
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}
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static int __init smp_psurge_kick_cpu(int nr)
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{
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unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
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unsigned long a, flags;
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int i, j;
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/* Defining this here is evil ... but I prefer hiding that
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* crap to avoid giving people ideas that they can do the
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* same.
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*/
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extern volatile unsigned int cpu_callin_map[NR_CPUS];
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/* may need to flush here if secondary bats aren't setup */
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for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
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asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
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asm volatile("sync");
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if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
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/* This is going to freeze the timeebase, we disable interrupts */
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local_irq_save(flags);
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out_be32(psurge_start, start);
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mb();
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psurge_set_ipi(nr);
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/*
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* We can't use udelay here because the timebase is now frozen.
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*/
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for (i = 0; i < 2000; ++i)
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asm volatile("nop" : : : "memory");
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psurge_clr_ipi(nr);
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/*
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* Also, because the timebase is frozen, we must not return to the
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* caller which will try to do udelay's etc... Instead, we wait -here-
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* for the CPU to callin.
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*/
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for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
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for (j = 1; j < 10000; j++)
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asm volatile("nop" : : : "memory");
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asm volatile("sync" : : : "memory");
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}
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if (!cpu_callin_map[nr])
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goto stuck;
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/* And we do the TB sync here too for standard dual CPU cards */
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if (psurge_type == PSURGE_DUAL) {
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while(!tb_req)
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barrier();
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tb_req = 0;
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mb();
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timebase = get_tb();
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mb();
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while (timebase)
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barrier();
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mb();
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}
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stuck:
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/* now interrupt the secondary, restarting both TBs */
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if (psurge_type == PSURGE_DUAL)
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psurge_set_ipi(1);
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if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
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return 0;
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}
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static struct irqaction psurge_irqaction = {
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.handler = psurge_ipi_intr,
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.flags = IRQF_PERCPU | IRQF_NO_THREAD,
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.name = "primary IPI",
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};
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static void __init smp_psurge_setup_cpu(int cpu_nr)
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{
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if (cpu_nr != 0 || !psurge_start)
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return;
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/* reset the entry point so if we get another intr we won't
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* try to startup again */
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out_be32(psurge_start, 0x100);
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if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
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printk(KERN_ERR "Couldn't get primary IPI interrupt");
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}
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void __init smp_psurge_take_timebase(void)
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{
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if (psurge_type != PSURGE_DUAL)
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return;
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tb_req = 1;
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mb();
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while (!timebase)
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barrier();
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mb();
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set_tb(timebase >> 32, timebase & 0xffffffff);
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timebase = 0;
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mb();
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set_dec(tb_ticks_per_jiffy/2);
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}
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void __init smp_psurge_give_timebase(void)
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{
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/* Nothing to do here */
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}
|
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|
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/* PowerSurge-style Macs */
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struct smp_ops_t psurge_smp_ops = {
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.message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
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.cause_ipi = smp_psurge_cause_ipi,
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.cause_nmi_ipi = NULL,
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.probe = smp_psurge_probe,
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.kick_cpu = smp_psurge_kick_cpu,
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.setup_cpu = smp_psurge_setup_cpu,
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.give_timebase = smp_psurge_give_timebase,
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.take_timebase = smp_psurge_take_timebase,
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};
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#endif /* CONFIG_PPC_PMAC32_PSURGE */
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|
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/*
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* Core 99 and later support
|
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*/
|
|
|
|
|
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static void smp_core99_give_timebase(void)
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{
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unsigned long flags;
|
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|
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local_irq_save(flags);
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|
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while(!tb_req)
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barrier();
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tb_req = 0;
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(*pmac_tb_freeze)(1);
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mb();
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timebase = get_tb();
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mb();
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while (timebase)
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barrier();
|
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mb();
|
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(*pmac_tb_freeze)(0);
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mb();
|
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|
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local_irq_restore(flags);
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}
|
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|
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|
|
static void smp_core99_take_timebase(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
tb_req = 1;
|
|
mb();
|
|
while (!timebase)
|
|
barrier();
|
|
mb();
|
|
set_tb(timebase >> 32, timebase & 0xffffffff);
|
|
timebase = 0;
|
|
mb();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
#ifdef CONFIG_PPC64
|
|
/*
|
|
* G5s enable/disable the timebase via an i2c-connected clock chip.
|
|
*/
|
|
static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
|
|
static u8 pmac_tb_pulsar_addr;
|
|
|
|
static void smp_core99_cypress_tb_freeze(int freeze)
|
|
{
|
|
u8 data;
|
|
int rc;
|
|
|
|
/* Strangely, the device-tree says address is 0xd2, but darwin
|
|
* accesses 0xd0 ...
|
|
*/
|
|
pmac_i2c_setmode(pmac_tb_clock_chip_host,
|
|
pmac_i2c_mode_combined);
|
|
rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
|
|
0xd0 | pmac_i2c_read,
|
|
1, 0x81, &data, 1);
|
|
if (rc != 0)
|
|
goto bail;
|
|
|
|
data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
|
|
|
|
pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
|
|
rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
|
|
0xd0 | pmac_i2c_write,
|
|
1, 0x81, &data, 1);
|
|
|
|
bail:
|
|
if (rc != 0) {
|
|
printk("Cypress Timebase %s rc: %d\n",
|
|
freeze ? "freeze" : "unfreeze", rc);
|
|
panic("Timebase freeze failed !\n");
|
|
}
|
|
}
|
|
|
|
|
|
static void smp_core99_pulsar_tb_freeze(int freeze)
|
|
{
|
|
u8 data;
|
|
int rc;
|
|
|
|
pmac_i2c_setmode(pmac_tb_clock_chip_host,
|
|
pmac_i2c_mode_combined);
|
|
rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
|
|
pmac_tb_pulsar_addr | pmac_i2c_read,
|
|
1, 0x2e, &data, 1);
|
|
if (rc != 0)
|
|
goto bail;
|
|
|
|
data = (data & 0x88) | (freeze ? 0x11 : 0x22);
|
|
|
|
pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
|
|
rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
|
|
pmac_tb_pulsar_addr | pmac_i2c_write,
|
|
1, 0x2e, &data, 1);
|
|
bail:
|
|
if (rc != 0) {
|
|
printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
|
|
freeze ? "freeze" : "unfreeze", rc);
|
|
panic("Timebase freeze failed !\n");
|
|
}
|
|
}
|
|
|
|
static void __init smp_core99_setup_i2c_hwsync(int ncpus)
|
|
{
|
|
struct device_node *cc = NULL;
|
|
struct device_node *p;
|
|
const char *name = NULL;
|
|
const u32 *reg;
|
|
int ok;
|
|
|
|
/* Look for the clock chip */
|
|
for_each_node_by_name(cc, "i2c-hwclock") {
|
|
p = of_get_parent(cc);
|
|
ok = p && of_device_is_compatible(p, "uni-n-i2c");
|
|
of_node_put(p);
|
|
if (!ok)
|
|
continue;
|
|
|
|
pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
|
|
if (pmac_tb_clock_chip_host == NULL)
|
|
continue;
|
|
reg = of_get_property(cc, "reg", NULL);
|
|
if (reg == NULL)
|
|
continue;
|
|
switch (*reg) {
|
|
case 0xd2:
|
|
if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
|
|
pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
|
|
pmac_tb_pulsar_addr = 0xd2;
|
|
name = "Pulsar";
|
|
} else if (of_device_is_compatible(cc, "cy28508")) {
|
|
pmac_tb_freeze = smp_core99_cypress_tb_freeze;
|
|
name = "Cypress";
|
|
}
|
|
break;
|
|
case 0xd4:
|
|
pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
|
|
pmac_tb_pulsar_addr = 0xd4;
|
|
name = "Pulsar";
|
|
break;
|
|
}
|
|
if (pmac_tb_freeze != NULL)
|
|
break;
|
|
}
|
|
if (pmac_tb_freeze != NULL) {
|
|
/* Open i2c bus for synchronous access */
|
|
if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
|
|
printk(KERN_ERR "Failed top open i2c bus for clock"
|
|
" sync, fallback to software sync !\n");
|
|
goto no_i2c_sync;
|
|
}
|
|
printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
|
|
name);
|
|
return;
|
|
}
|
|
no_i2c_sync:
|
|
pmac_tb_freeze = NULL;
|
|
pmac_tb_clock_chip_host = NULL;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Newer G5s uses a platform function
|
|
*/
|
|
|
|
static void smp_core99_pfunc_tb_freeze(int freeze)
|
|
{
|
|
struct device_node *cpus;
|
|
struct pmf_args args;
|
|
|
|
cpus = of_find_node_by_path("/cpus");
|
|
BUG_ON(cpus == NULL);
|
|
args.count = 1;
|
|
args.u[0].v = !freeze;
|
|
pmf_call_function(cpus, "cpu-timebase", &args);
|
|
of_node_put(cpus);
|
|
}
|
|
|
|
#else /* CONFIG_PPC64 */
|
|
|
|
/*
|
|
* SMP G4 use a GPIO to enable/disable the timebase.
|
|
*/
|
|
|
|
static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */
|
|
|
|
static void smp_core99_gpio_tb_freeze(int freeze)
|
|
{
|
|
if (freeze)
|
|
pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
|
|
else
|
|
pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
|
|
pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
|
|
}
|
|
|
|
|
|
#endif /* !CONFIG_PPC64 */
|
|
|
|
/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
|
|
volatile static long int core99_l2_cache;
|
|
volatile static long int core99_l3_cache;
|
|
|
|
static void core99_init_caches(int cpu)
|
|
{
|
|
#ifndef CONFIG_PPC64
|
|
if (!cpu_has_feature(CPU_FTR_L2CR))
|
|
return;
|
|
|
|
if (cpu == 0) {
|
|
core99_l2_cache = _get_L2CR();
|
|
printk("CPU0: L2CR is %lx\n", core99_l2_cache);
|
|
} else {
|
|
printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
|
|
_set_L2CR(0);
|
|
_set_L2CR(core99_l2_cache);
|
|
printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
|
|
}
|
|
|
|
if (!cpu_has_feature(CPU_FTR_L3CR))
|
|
return;
|
|
|
|
if (cpu == 0){
|
|
core99_l3_cache = _get_L3CR();
|
|
printk("CPU0: L3CR is %lx\n", core99_l3_cache);
|
|
} else {
|
|
printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
|
|
_set_L3CR(0);
|
|
_set_L3CR(core99_l3_cache);
|
|
printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
|
|
}
|
|
#endif /* !CONFIG_PPC64 */
|
|
}
|
|
|
|
static void __init smp_core99_setup(int ncpus)
|
|
{
|
|
#ifdef CONFIG_PPC64
|
|
|
|
/* i2c based HW sync on some G5s */
|
|
if (of_machine_is_compatible("PowerMac7,2") ||
|
|
of_machine_is_compatible("PowerMac7,3") ||
|
|
of_machine_is_compatible("RackMac3,1"))
|
|
smp_core99_setup_i2c_hwsync(ncpus);
|
|
|
|
/* pfunc based HW sync on recent G5s */
|
|
if (pmac_tb_freeze == NULL) {
|
|
struct device_node *cpus =
|
|
of_find_node_by_path("/cpus");
|
|
if (cpus &&
|
|
of_get_property(cpus, "platform-cpu-timebase", NULL)) {
|
|
pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
|
|
printk(KERN_INFO "Processor timebase sync using"
|
|
" platform function\n");
|
|
}
|
|
}
|
|
|
|
#else /* CONFIG_PPC64 */
|
|
|
|
/* GPIO based HW sync on ppc32 Core99 */
|
|
if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
|
|
struct device_node *cpu;
|
|
const u32 *tbprop = NULL;
|
|
|
|
core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */
|
|
cpu = of_find_node_by_type(NULL, "cpu");
|
|
if (cpu != NULL) {
|
|
tbprop = of_get_property(cpu, "timebase-enable", NULL);
|
|
if (tbprop)
|
|
core99_tb_gpio = *tbprop;
|
|
of_node_put(cpu);
|
|
}
|
|
pmac_tb_freeze = smp_core99_gpio_tb_freeze;
|
|
printk(KERN_INFO "Processor timebase sync using"
|
|
" GPIO 0x%02x\n", core99_tb_gpio);
|
|
}
|
|
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
/* No timebase sync, fallback to software */
|
|
if (pmac_tb_freeze == NULL) {
|
|
smp_ops->give_timebase = smp_generic_give_timebase;
|
|
smp_ops->take_timebase = smp_generic_take_timebase;
|
|
printk(KERN_INFO "Processor timebase sync using software\n");
|
|
}
|
|
|
|
#ifndef CONFIG_PPC64
|
|
{
|
|
int i;
|
|
|
|
/* XXX should get this from reg properties */
|
|
for (i = 1; i < ncpus; ++i)
|
|
set_hard_smp_processor_id(i, i);
|
|
}
|
|
#endif
|
|
|
|
/* 32 bits SMP can't NAP */
|
|
if (!of_machine_is_compatible("MacRISC4"))
|
|
powersave_nap = 0;
|
|
}
|
|
|
|
static void __init smp_core99_probe(void)
|
|
{
|
|
struct device_node *cpus;
|
|
int ncpus = 0;
|
|
|
|
if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
|
|
|
|
/* Count CPUs in the device-tree */
|
|
for_each_node_by_type(cpus, "cpu")
|
|
++ncpus;
|
|
|
|
printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
|
|
|
|
/* Nothing more to do if less than 2 of them */
|
|
if (ncpus <= 1)
|
|
return;
|
|
|
|
/* We need to perform some early initialisations before we can start
|
|
* setting up SMP as we are running before initcalls
|
|
*/
|
|
pmac_pfunc_base_install();
|
|
pmac_i2c_init();
|
|
|
|
/* Setup various bits like timebase sync method, ability to nap, ... */
|
|
smp_core99_setup(ncpus);
|
|
|
|
/* Install IPIs */
|
|
mpic_request_ipis();
|
|
|
|
/* Collect l2cr and l3cr values from CPU 0 */
|
|
core99_init_caches(0);
|
|
}
|
|
|
|
static int smp_core99_kick_cpu(int nr)
|
|
{
|
|
unsigned int save_vector;
|
|
unsigned long target, flags;
|
|
unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
|
|
|
|
if (nr < 0 || nr > 3)
|
|
return -ENOENT;
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("smp_core99_kick_cpu", 0x346);
|
|
|
|
local_irq_save(flags);
|
|
|
|
/* Save reset vector */
|
|
save_vector = *vector;
|
|
|
|
/* Setup fake reset vector that does
|
|
* b __secondary_start_pmac_0 + nr*8
|
|
*/
|
|
target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
|
|
patch_branch(vector, target, BRANCH_SET_LINK);
|
|
|
|
/* Put some life in our friend */
|
|
pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
|
|
|
|
/* FIXME: We wait a bit for the CPU to take the exception, I should
|
|
* instead wait for the entry code to set something for me. Well,
|
|
* ideally, all that crap will be done in prom.c and the CPU left
|
|
* in a RAM-based wait loop like CHRP.
|
|
*/
|
|
mdelay(1);
|
|
|
|
/* Restore our exception vector */
|
|
*vector = save_vector;
|
|
flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
|
|
|
|
local_irq_restore(flags);
|
|
if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void smp_core99_setup_cpu(int cpu_nr)
|
|
{
|
|
/* Setup L2/L3 */
|
|
if (cpu_nr != 0)
|
|
core99_init_caches(cpu_nr);
|
|
|
|
/* Setup openpic */
|
|
mpic_setup_this_cpu();
|
|
}
|
|
|
|
#ifdef CONFIG_PPC64
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
static unsigned int smp_core99_host_open;
|
|
|
|
static int smp_core99_cpu_prepare(unsigned int cpu)
|
|
{
|
|
int rc;
|
|
|
|
/* Open i2c bus if it was used for tb sync */
|
|
if (pmac_tb_clock_chip_host && !smp_core99_host_open) {
|
|
rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
|
|
if (rc) {
|
|
pr_err("Failed to open i2c bus for time sync\n");
|
|
return notifier_from_errno(rc);
|
|
}
|
|
smp_core99_host_open = 1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int smp_core99_cpu_online(unsigned int cpu)
|
|
{
|
|
/* Close i2c bus if it was used for tb sync */
|
|
if (pmac_tb_clock_chip_host && smp_core99_host_open) {
|
|
pmac_i2c_close(pmac_tb_clock_chip_host);
|
|
smp_core99_host_open = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|
|
|
|
static void __init smp_core99_bringup_done(void)
|
|
{
|
|
extern void g5_phy_disable_cpu1(void);
|
|
|
|
/* Close i2c bus if it was used for tb sync */
|
|
if (pmac_tb_clock_chip_host)
|
|
pmac_i2c_close(pmac_tb_clock_chip_host);
|
|
|
|
/* If we didn't start the second CPU, we must take
|
|
* it off the bus.
|
|
*/
|
|
if (of_machine_is_compatible("MacRISC4") &&
|
|
num_online_cpus() < 2) {
|
|
set_cpu_present(1, false);
|
|
g5_phy_disable_cpu1();
|
|
}
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE,
|
|
"powerpc/pmac:prepare", smp_core99_cpu_prepare,
|
|
NULL);
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online",
|
|
smp_core99_cpu_online, NULL);
|
|
#endif
|
|
|
|
if (ppc_md.progress)
|
|
ppc_md.progress("smp_core99_bringup_done", 0x349);
|
|
}
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
|
|
static int smp_core99_cpu_disable(void)
|
|
{
|
|
int rc = generic_cpu_disable();
|
|
if (rc)
|
|
return rc;
|
|
|
|
mpic_cpu_set_priority(0xf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC32
|
|
|
|
static void pmac_cpu_die(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
local_irq_disable();
|
|
idle_task_exit();
|
|
pr_debug("CPU%d offline\n", cpu);
|
|
generic_set_cpu_dead(cpu);
|
|
smp_wmb();
|
|
mb();
|
|
low_cpu_die();
|
|
}
|
|
|
|
#else /* CONFIG_PPC32 */
|
|
|
|
static void pmac_cpu_die(void)
|
|
{
|
|
int cpu = smp_processor_id();
|
|
|
|
local_irq_disable();
|
|
idle_task_exit();
|
|
|
|
/*
|
|
* turn off as much as possible, we'll be
|
|
* kicked out as this will only be invoked
|
|
* on core99 platforms for now ...
|
|
*/
|
|
|
|
printk(KERN_INFO "CPU#%d offline\n", cpu);
|
|
generic_set_cpu_dead(cpu);
|
|
smp_wmb();
|
|
|
|
/*
|
|
* Re-enable interrupts. The NAP code needs to enable them
|
|
* anyways, do it now so we deal with the case where one already
|
|
* happened while soft-disabled.
|
|
* We shouldn't get any external interrupts, only decrementer, and the
|
|
* decrementer handler is safe for use on offline CPUs
|
|
*/
|
|
local_irq_enable();
|
|
|
|
while (1) {
|
|
/* let's not take timer interrupts too often ... */
|
|
set_dec(0x7fffffff);
|
|
|
|
/* Enter NAP mode */
|
|
power4_idle();
|
|
}
|
|
}
|
|
|
|
#endif /* else CONFIG_PPC32 */
|
|
#endif /* CONFIG_HOTPLUG_CPU */
|
|
|
|
/* Core99 Macs (dual G4s and G5s) */
|
|
static struct smp_ops_t core99_smp_ops = {
|
|
.message_pass = smp_mpic_message_pass,
|
|
.probe = smp_core99_probe,
|
|
#ifdef CONFIG_PPC64
|
|
.bringup_done = smp_core99_bringup_done,
|
|
#endif
|
|
.kick_cpu = smp_core99_kick_cpu,
|
|
.setup_cpu = smp_core99_setup_cpu,
|
|
.give_timebase = smp_core99_give_timebase,
|
|
.take_timebase = smp_core99_take_timebase,
|
|
#if defined(CONFIG_HOTPLUG_CPU)
|
|
.cpu_disable = smp_core99_cpu_disable,
|
|
.cpu_die = generic_cpu_die,
|
|
#endif
|
|
};
|
|
|
|
void __init pmac_setup_smp(void)
|
|
{
|
|
struct device_node *np;
|
|
|
|
/* Check for Core99 */
|
|
np = of_find_node_by_name(NULL, "uni-n");
|
|
if (!np)
|
|
np = of_find_node_by_name(NULL, "u3");
|
|
if (!np)
|
|
np = of_find_node_by_name(NULL, "u4");
|
|
if (np) {
|
|
of_node_put(np);
|
|
smp_ops = &core99_smp_ops;
|
|
}
|
|
#ifdef CONFIG_PPC_PMAC32_PSURGE
|
|
else {
|
|
/* We have to set bits in cpu_possible_mask here since the
|
|
* secondary CPU(s) aren't in the device tree. Various
|
|
* things won't be initialized for CPUs not in the possible
|
|
* map, so we really need to fix it up here.
|
|
*/
|
|
int cpu;
|
|
|
|
for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
|
|
set_cpu_possible(cpu, true);
|
|
smp_ops = &psurge_smp_ops;
|
|
}
|
|
#endif /* CONFIG_PPC_PMAC32_PSURGE */
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
ppc_md.cpu_die = pmac_cpu_die;
|
|
#endif
|
|
}
|
|
|
|
|