622 lines
16 KiB
C
622 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Alchemy Db1550/Pb1550 board support
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*
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* (c) 2011 Manuel Lauss <manuel.lauss@googlemail.com>
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/gpio.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/gpio-au1000.h>
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#include <asm/mach-au1x00/au1xxx_eth.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#include <asm/mach-au1x00/au1550_spi.h>
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#include <asm/mach-au1x00/au1550nd.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <prom.h>
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#include "platform.h"
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static void __init db1550_hw_setup(void)
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{
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void __iomem *base;
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unsigned long v;
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/* complete pin setup: assign GPIO16 to PSC0_SYNC1 (SPI cs# line)
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* as well as PSC1_SYNC for AC97 on PB1550.
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*/
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v = alchemy_rdsys(AU1000_SYS_PINFUNC);
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alchemy_wrsys(v | 1 | SYS_PF_PSC1_S1, AU1000_SYS_PINFUNC);
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/* reset the AC97 codec now, the reset time in the psc-ac97 driver
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* is apparently too short although it's ridiculous as it is.
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*/
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base = (void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR);
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__raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE,
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base + PSC_SEL_OFFSET);
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__raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET);
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wmb();
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__raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET);
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wmb();
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}
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int __init db1550_board_setup(void)
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{
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unsigned short whoami;
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bcsr_init(DB1550_BCSR_PHYS_ADDR,
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DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS);
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whoami = bcsr_read(BCSR_WHOAMI); /* PB1550 hexled offset differs */
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switch (BCSR_WHOAMI_BOARD(whoami)) {
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case BCSR_WHOAMI_PB1550_SDR:
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case BCSR_WHOAMI_PB1550_DDR:
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bcsr_init(PB1550_BCSR_PHYS_ADDR,
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PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
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case BCSR_WHOAMI_DB1550:
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break;
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default:
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return -ENODEV;
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}
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pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d " \
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"Daughtercard ID %d\n", get_system_type(),
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(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
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db1550_hw_setup();
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return 0;
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}
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/*****************************************************************************/
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static struct mtd_partition db1550_spiflash_parts[] = {
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{
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.name = "spi_flash",
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.offset = 0,
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.size = MTDPART_SIZ_FULL,
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},
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};
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static struct flash_platform_data db1550_spiflash_data = {
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.name = "s25fl010",
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.parts = db1550_spiflash_parts,
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.nr_parts = ARRAY_SIZE(db1550_spiflash_parts),
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.type = "m25p10",
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};
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static struct spi_board_info db1550_spi_devs[] __initdata = {
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{
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/* TI TMP121AIDBVR temp sensor */
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.modalias = "tmp121",
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.max_speed_hz = 2400000,
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.bus_num = 0,
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.chip_select = 0,
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.mode = SPI_MODE_0,
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},
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{
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/* Spansion S25FL001D0FMA SPI flash */
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.modalias = "m25p80",
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.max_speed_hz = 2400000,
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.bus_num = 0,
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.chip_select = 1,
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.mode = SPI_MODE_0,
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.platform_data = &db1550_spiflash_data,
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},
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};
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static struct i2c_board_info db1550_i2c_devs[] __initdata = {
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{ I2C_BOARD_INFO("24c04", 0x52),}, /* AT24C04-10 I2C eeprom */
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{ I2C_BOARD_INFO("ne1619", 0x2d),}, /* adm1025-compat hwmon */
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{ I2C_BOARD_INFO("wm8731", 0x1b),}, /* I2S audio codec WM8731 */
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};
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/**********************************************************************/
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static void au1550_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
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ioaddr &= 0xffffff00;
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if (ctrl & NAND_CLE) {
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ioaddr += MEM_STNAND_CMD;
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} else if (ctrl & NAND_ALE) {
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ioaddr += MEM_STNAND_ADDR;
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} else {
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/* assume we want to r/w real data by default */
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ioaddr += MEM_STNAND_DATA;
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}
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this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
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if (cmd != NAND_CMD_NONE) {
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__raw_writeb(cmd, this->IO_ADDR_W);
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wmb();
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}
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}
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static int au1550_nand_device_ready(struct mtd_info *mtd)
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{
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return alchemy_rdsmem(AU1000_MEM_STSTAT) & 1;
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}
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static struct mtd_partition db1550_nand_parts[] = {
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{
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.name = "NAND FS 0",
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.offset = 0,
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.size = 8 * 1024 * 1024,
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},
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{
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.name = "NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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},
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};
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struct platform_nand_data db1550_nand_platdata = {
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.chip = {
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.nr_chips = 1,
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.chip_offset = 0,
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.nr_partitions = ARRAY_SIZE(db1550_nand_parts),
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.partitions = db1550_nand_parts,
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.chip_delay = 20,
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},
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.ctrl = {
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.dev_ready = au1550_nand_device_ready,
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.cmd_ctrl = au1550_nand_cmd_ctrl,
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},
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};
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static struct resource db1550_nand_res[] = {
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[0] = {
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.start = 0x20000000,
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.end = 0x200000ff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device db1550_nand_dev = {
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.name = "gen_nand",
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.num_resources = ARRAY_SIZE(db1550_nand_res),
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.resource = db1550_nand_res,
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.id = -1,
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.dev = {
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.platform_data = &db1550_nand_platdata,
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}
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};
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static struct au1550nd_platdata pb1550_nand_pd = {
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.parts = db1550_nand_parts,
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.num_parts = ARRAY_SIZE(db1550_nand_parts),
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.devwidth = 0, /* x8 NAND default, needs fixing up */
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};
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static struct platform_device pb1550_nand_dev = {
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.name = "au1550-nand",
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.id = -1,
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.resource = db1550_nand_res,
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.num_resources = ARRAY_SIZE(db1550_nand_res),
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.dev = {
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.platform_data = &pb1550_nand_pd,
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},
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};
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static void __init pb1550_nand_setup(void)
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{
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int boot_swapboot = (alchemy_rdsmem(AU1000_MEM_STSTAT) & (0x7 << 1)) |
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((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
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gpio_direction_input(206); /* de-assert NAND CS# */
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switch (boot_swapboot) {
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case 0: case 2: case 8: case 0xC: case 0xD:
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/* x16 NAND Flash */
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pb1550_nand_pd.devwidth = 1;
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/* fallthrough */
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case 1: case 3: case 9: case 0xE: case 0xF:
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/* x8 NAND, already set up */
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platform_device_register(&pb1550_nand_dev);
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}
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}
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/**********************************************************************/
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static struct resource au1550_psc0_res[] = {
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[0] = {
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.start = AU1550_PSC0_PHYS_ADDR,
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.end = AU1550_PSC0_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1550_PSC0_INT,
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.end = AU1550_PSC0_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = AU1550_DSCR_CMD0_PSC0_TX,
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.end = AU1550_DSCR_CMD0_PSC0_TX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = AU1550_DSCR_CMD0_PSC0_RX,
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.end = AU1550_DSCR_CMD0_PSC0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static void db1550_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
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{
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if (cs)
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bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SPISEL);
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else
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bcsr_mod(BCSR_BOARD, BCSR_BOARD_SPISEL, 0);
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}
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static struct au1550_spi_info db1550_spi_platdata = {
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.mainclk_hz = 48000000, /* PSC0 clock: max. 2.4MHz SPI clk */
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.num_chipselect = 2,
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.activate_cs = db1550_spi_cs_en,
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};
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static u64 spi_dmamask = DMA_BIT_MASK(32);
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static struct platform_device db1550_spi_dev = {
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.dev = {
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.dma_mask = &spi_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &db1550_spi_platdata,
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},
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.name = "au1550-spi",
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.id = 0, /* bus number */
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.num_resources = ARRAY_SIZE(au1550_psc0_res),
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.resource = au1550_psc0_res,
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};
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/**********************************************************************/
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static struct resource au1550_psc1_res[] = {
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[0] = {
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.start = AU1550_PSC1_PHYS_ADDR,
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.end = AU1550_PSC1_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1550_PSC1_INT,
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.end = AU1550_PSC1_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = AU1550_DSCR_CMD0_PSC1_TX,
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.end = AU1550_DSCR_CMD0_PSC1_TX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = AU1550_DSCR_CMD0_PSC1_RX,
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.end = AU1550_DSCR_CMD0_PSC1_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device db1550_ac97_dev = {
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.name = "au1xpsc_ac97",
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.id = 1, /* PSC ID */
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.num_resources = ARRAY_SIZE(au1550_psc1_res),
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.resource = au1550_psc1_res,
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};
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static struct resource au1550_psc2_res[] = {
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[0] = {
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.start = AU1550_PSC2_PHYS_ADDR,
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.end = AU1550_PSC2_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1550_PSC2_INT,
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.end = AU1550_PSC2_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = AU1550_DSCR_CMD0_PSC2_TX,
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.end = AU1550_DSCR_CMD0_PSC2_TX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = AU1550_DSCR_CMD0_PSC2_RX,
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.end = AU1550_DSCR_CMD0_PSC2_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device db1550_i2c_dev = {
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.name = "au1xpsc_smbus",
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.id = 0, /* bus number */
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.num_resources = ARRAY_SIZE(au1550_psc2_res),
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.resource = au1550_psc2_res,
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};
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/**********************************************************************/
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static struct resource au1550_psc3_res[] = {
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[0] = {
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.start = AU1550_PSC3_PHYS_ADDR,
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.end = AU1550_PSC3_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1550_PSC3_INT,
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.end = AU1550_PSC3_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = AU1550_DSCR_CMD0_PSC3_TX,
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.end = AU1550_DSCR_CMD0_PSC3_TX,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = AU1550_DSCR_CMD0_PSC3_RX,
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.end = AU1550_DSCR_CMD0_PSC3_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static struct platform_device db1550_i2s_dev = {
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.name = "au1xpsc_i2s",
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.id = 3, /* PSC ID */
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.num_resources = ARRAY_SIZE(au1550_psc3_res),
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.resource = au1550_psc3_res,
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};
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/**********************************************************************/
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static struct platform_device db1550_stac_dev = {
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.name = "ac97-codec",
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.id = 1, /* on PSC1 */
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};
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static struct platform_device db1550_ac97dma_dev = {
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.name = "au1xpsc-pcm",
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.id = 1, /* on PSC3 */
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};
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static struct platform_device db1550_i2sdma_dev = {
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.name = "au1xpsc-pcm",
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.id = 3, /* on PSC3 */
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};
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static struct platform_device db1550_sndac97_dev = {
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.name = "db1550-ac97",
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};
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static struct platform_device db1550_sndi2s_dev = {
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.name = "db1550-i2s",
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};
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/**********************************************************************/
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static int db1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
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{
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if ((slot < 11) || (slot > 13) || pin == 0)
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return -1;
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if (slot == 11)
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return (pin == 1) ? AU1550_PCI_INTC : 0xff;
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if (slot == 12) {
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switch (pin) {
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case 1: return AU1550_PCI_INTB;
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case 2: return AU1550_PCI_INTC;
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case 3: return AU1550_PCI_INTD;
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case 4: return AU1550_PCI_INTA;
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}
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}
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if (slot == 13) {
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switch (pin) {
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case 1: return AU1550_PCI_INTA;
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case 2: return AU1550_PCI_INTB;
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case 3: return AU1550_PCI_INTC;
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case 4: return AU1550_PCI_INTD;
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}
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}
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return -1;
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}
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static int pb1550_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
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{
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if ((slot < 12) || (slot > 13) || pin == 0)
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return -1;
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if (slot == 12) {
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switch (pin) {
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case 1: return AU1500_PCI_INTB;
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case 2: return AU1500_PCI_INTC;
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case 3: return AU1500_PCI_INTD;
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case 4: return AU1500_PCI_INTA;
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}
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}
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if (slot == 13) {
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switch (pin) {
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case 1: return AU1500_PCI_INTA;
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case 2: return AU1500_PCI_INTB;
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case 3: return AU1500_PCI_INTC;
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case 4: return AU1500_PCI_INTD;
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}
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}
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return -1;
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}
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static struct resource alchemy_pci_host_res[] = {
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[0] = {
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.start = AU1500_PCI_PHYS_ADDR,
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.end = AU1500_PCI_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct alchemy_pci_platdata db1550_pci_pd = {
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.board_map_irq = db1550_map_pci_irq,
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};
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static struct platform_device db1550_pci_host_dev = {
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.dev.platform_data = &db1550_pci_pd,
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.name = "alchemy-pci",
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.id = 0,
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.num_resources = ARRAY_SIZE(alchemy_pci_host_res),
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.resource = alchemy_pci_host_res,
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};
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/**********************************************************************/
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static struct platform_device *db1550_devs[] __initdata = {
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&db1550_i2c_dev,
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&db1550_ac97_dev,
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&db1550_spi_dev,
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&db1550_i2s_dev,
|
|
&db1550_stac_dev,
|
|
&db1550_ac97dma_dev,
|
|
&db1550_i2sdma_dev,
|
|
&db1550_sndac97_dev,
|
|
&db1550_sndi2s_dev,
|
|
};
|
|
|
|
/* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
|
|
int __init db1550_pci_setup(int id)
|
|
{
|
|
if (id)
|
|
db1550_pci_pd.board_map_irq = pb1550_map_pci_irq;
|
|
return platform_device_register(&db1550_pci_host_dev);
|
|
}
|
|
|
|
static void __init db1550_devices(void)
|
|
{
|
|
alchemy_gpio_direction_output(203, 0); /* red led on */
|
|
|
|
irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH); /* CD0# */
|
|
irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH); /* CD1# */
|
|
irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW); /* CARD0# */
|
|
irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW); /* CARD1# */
|
|
irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
|
|
irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
|
|
|
|
db1x_register_pcmcia_socket(
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR,
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
|
|
AU1550_GPIO3_INT, 0,
|
|
/*AU1550_GPIO21_INT*/0, 0, 0);
|
|
|
|
db1x_register_pcmcia_socket(
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004000000,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x004400000 - 1,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004000000,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x004010000 - 1,
|
|
AU1550_GPIO5_INT, 1,
|
|
/*AU1550_GPIO22_INT*/0, 0, 1);
|
|
|
|
platform_device_register(&db1550_nand_dev);
|
|
|
|
alchemy_gpio_direction_output(202, 0); /* green led on */
|
|
}
|
|
|
|
static void __init pb1550_devices(void)
|
|
{
|
|
irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_LEVEL_LOW);
|
|
irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_LEVEL_LOW);
|
|
irq_set_irq_type(AU1550_GPIO201_205_INT, IRQ_TYPE_LEVEL_HIGH);
|
|
|
|
/* enable both PCMCIA card irqs in the shared line */
|
|
alchemy_gpio2_enable_int(201); /* socket 0 card irq */
|
|
alchemy_gpio2_enable_int(202); /* socket 1 card irq */
|
|
|
|
/* Pb1550, like all others, also has statuschange irqs; however they're
|
|
* wired up on one of the Au1550's shared GPIO201_205 line, which also
|
|
* services the PCMCIA card interrupts. So we ignore statuschange and
|
|
* use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
|
|
* drivers are used to shared irqs and b) statuschange isn't really use-
|
|
* ful anyway.
|
|
*/
|
|
db1x_register_pcmcia_socket(
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR,
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x000010000 - 1,
|
|
AU1550_GPIO201_205_INT, AU1550_GPIO0_INT, 0, 0, 0);
|
|
|
|
db1x_register_pcmcia_socket(
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
|
|
AU1000_PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008000000,
|
|
AU1000_PCMCIA_MEM_PHYS_ADDR + 0x008400000 - 1,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008000000,
|
|
AU1000_PCMCIA_IO_PHYS_ADDR + 0x008010000 - 1,
|
|
AU1550_GPIO201_205_INT, AU1550_GPIO1_INT, 0, 0, 1);
|
|
|
|
pb1550_nand_setup();
|
|
}
|
|
|
|
int __init db1550_dev_setup(void)
|
|
{
|
|
int swapped, id;
|
|
struct clk *c;
|
|
|
|
id = (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI)) != BCSR_WHOAMI_DB1550);
|
|
|
|
i2c_register_board_info(0, db1550_i2c_devs,
|
|
ARRAY_SIZE(db1550_i2c_devs));
|
|
spi_register_board_info(db1550_spi_devs,
|
|
ARRAY_SIZE(db1550_i2c_devs));
|
|
|
|
c = clk_get(NULL, "psc0_intclk");
|
|
if (!IS_ERR(c)) {
|
|
clk_set_rate(c, 50000000);
|
|
clk_prepare_enable(c);
|
|
clk_put(c);
|
|
}
|
|
c = clk_get(NULL, "psc2_intclk");
|
|
if (!IS_ERR(c)) {
|
|
clk_set_rate(c, db1550_spi_platdata.mainclk_hz);
|
|
clk_prepare_enable(c);
|
|
clk_put(c);
|
|
}
|
|
|
|
/* Audio PSC clock is supplied by codecs (PSC1, 3) FIXME: platdata!! */
|
|
__raw_writel(PSC_SEL_CLK_SERCLK,
|
|
(void __iomem *)KSEG1ADDR(AU1550_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
|
|
wmb();
|
|
__raw_writel(PSC_SEL_CLK_SERCLK,
|
|
(void __iomem *)KSEG1ADDR(AU1550_PSC3_PHYS_ADDR) + PSC_SEL_OFFSET);
|
|
wmb();
|
|
/* SPI/I2C use internally supplied 50MHz source */
|
|
__raw_writel(PSC_SEL_CLK_INTCLK,
|
|
(void __iomem *)KSEG1ADDR(AU1550_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET);
|
|
wmb();
|
|
__raw_writel(PSC_SEL_CLK_INTCLK,
|
|
(void __iomem *)KSEG1ADDR(AU1550_PSC2_PHYS_ADDR) + PSC_SEL_OFFSET);
|
|
wmb();
|
|
|
|
id ? pb1550_devices() : db1550_devices();
|
|
|
|
swapped = bcsr_read(BCSR_STATUS) &
|
|
(id ? BCSR_STATUS_PB1550_SWAPBOOT : BCSR_STATUS_DB1000_SWAPBOOT);
|
|
db1x_register_norflash(128 << 20, 4, swapped);
|
|
|
|
return platform_add_devices(db1550_devs, ARRAY_SIZE(db1550_devs));
|
|
}
|