117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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extern void erratum_a008850_post(void);
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo_override;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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{1, 1666, 0, 12, 7, 0x07090800, 0x00000000,},
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{1, 1900, 0, 12, 7, 0x07090800, 0x00000000,},
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{1, 2200, 0, 12, 7, 0x07090800, 0x00000000,},
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#endif
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#ifndef CONFIG_SYS_DDR_RAW_TIMING
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fsl_ddr_cfg_regs_t ddr_cfg_regs_1600 = {
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.cs[0].bnds = 0x0000007F,
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.cs[1].bnds = 0,
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.cs[2].bnds = 0,
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.cs[3].bnds = 0,
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.cs[0].config = 0x80040322,
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.cs[0].config_2 = 0,
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.cs[1].config = 0,
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.cs[1].config_2 = 0,
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.cs[2].config = 0,
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.cs[3].config = 0,
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.timing_cfg_3 = 0x010C1000,
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.timing_cfg_0 = 0x91550018,
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.timing_cfg_1 = 0xBBB48C42,
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.timing_cfg_2 = 0x0048C111,
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.ddr_sdram_cfg = 0xC50C0008,
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.ddr_sdram_cfg_2 = 0x00401100,
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.ddr_sdram_cfg_3 = 0,
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.ddr_sdram_mode = 0x03010210,
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.ddr_sdram_mode_2 = 0,
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.ddr_sdram_mode_3 = 0x00010210,
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.ddr_sdram_mode_4 = 0,
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.ddr_sdram_mode_5 = 0x00010210,
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.ddr_sdram_mode_6 = 0,
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.ddr_sdram_mode_7 = 0x00010210,
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.ddr_sdram_mode_8 = 0,
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.ddr_sdram_mode_9 = 0x00000500,
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.ddr_sdram_mode_10 = 0x04000000,
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.ddr_sdram_mode_11 = 0x00000400,
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.ddr_sdram_mode_12 = 0x04000000,
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.ddr_sdram_mode_13 = 0x00000400,
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.ddr_sdram_mode_14 = 0x04000000,
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.ddr_sdram_mode_15 = 0x00000400,
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.ddr_sdram_mode_16 = 0x04000000,
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.ddr_sdram_interval = 0x18600618,
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.ddr_data_init = 0xDEADBEEF,
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.ddr_sdram_clk_cntl = 0x03000000,
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.ddr_init_addr = 0,
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.ddr_init_ext_addr = 0,
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.timing_cfg_4 = 0x00000002,
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.timing_cfg_5 = 0x03401400,
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.timing_cfg_6 = 0,
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.timing_cfg_7 = 0x13300000,
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.timing_cfg_8 = 0x02115600,
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.timing_cfg_9 = 0,
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.ddr_zq_cntl = 0x8A090705,
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.ddr_wrlvl_cntl = 0x8675F607,
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.ddr_wrlvl_cntl_2 = 0x07090800,
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.ddr_wrlvl_cntl_3 = 0,
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.ddr_sr_cntr = 0,
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.ddr_sdram_rcw_1 = 0,
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.ddr_sdram_rcw_2 = 0,
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.ddr_cdr1 = 0x80040000,
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.ddr_cdr2 = 0x0000A181,
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.dq_map_0 = 0,
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.dq_map_1 = 0,
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.dq_map_2 = 0,
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.dq_map_3 = 0,
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.debug[28] = 0x00700046,
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};
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fixed_ddr_parm_t fixed_ddr_parm_0[] = {
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{1550, 1650, &ddr_cfg_regs_1600},
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{0, 0, NULL}
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};
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#endif
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#endif
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