319 lines
8.0 KiB
C
319 lines
8.0 KiB
C
/*
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* OMAP2 Power Management Routines
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Copyright (C) 2006-2008 Nokia Corporation
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*
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* Written by:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Tony Lindgren
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* Juha Yrjola
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* Amit Kucheria <amit.kucheria@nokia.com>
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* Igor Stoppa <igor.stoppa@nokia.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/interrupt.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <asm/fncpy.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <asm/system_misc.h>
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#include <linux/omap-dma.h>
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#include "soc.h"
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#include "common.h"
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#include "clock.h"
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#include "prm2xxx.h"
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#include "prm-regbits-24xx.h"
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#include "cm2xxx.h"
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#include "cm-regbits-24xx.h"
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#include "sdrc.h"
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#include "sram.h"
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#include "pm.h"
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#include "control.h"
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#include "powerdomain.h"
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#include "clockdomain.h"
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static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
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void __iomem *sdrc_power);
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static struct powerdomain *mpu_pwrdm, *core_pwrdm;
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static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
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static struct clk *osc_ck, *emul_ck;
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static int omap2_enter_full_retention(void)
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{
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u32 l;
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/* There is 1 reference hold for all children of the oscillator
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* clock, the following will remove it. If no one else uses the
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* oscillator itself it will be disabled if/when we enter retention
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* mode.
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*/
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clk_disable(osc_ck);
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/* Clear old wake-up events */
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/* REVISIT: These write to reserved bits? */
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omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
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pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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/* Workaround to kill USB */
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l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
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omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
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omap2_gpio_prepare_for_idle(0);
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/* One last check for pending IRQs to avoid extra latency due
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* to sleeping unnecessarily. */
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if (omap_irq_pending())
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goto no_sleep;
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/* Jump to SRAM suspend code */
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omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
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OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
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OMAP_SDRC_REGADDR(SDRC_POWER));
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no_sleep:
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omap2_gpio_resume_after_idle();
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clk_enable(osc_ck);
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/* clear CORE wake-up events */
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omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
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omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1);
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/* MPU domain wake events */
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omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x1);
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omap_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, 0x20);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
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return 0;
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}
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static int sti_console_enabled;
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static int omap2_allow_mpu_retention(void)
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{
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if (!omap2xxx_cm_mpu_retention_allowed())
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return 0;
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if (sti_console_enabled)
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return 0;
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return 1;
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}
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static void omap2_enter_mpu_retention(void)
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{
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const int zero = 0;
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/* The peripherals seem not to be able to wake up the MPU when
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* it is in retention mode. */
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if (omap2_allow_mpu_retention()) {
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/* REVISIT: These write to reserved bits? */
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omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0);
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omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0);
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omap_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0);
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/* Try to enter MPU retention */
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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} else {
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/* Block MPU retention */
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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}
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/* WFI */
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asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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}
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static int omap2_can_sleep(void)
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{
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if (omap2xxx_cm_fclks_active())
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return 0;
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if (__clk_is_enabled(osc_ck))
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return 0;
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if (omap_dma_running())
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return 0;
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return 1;
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}
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static void omap2_pm_idle(void)
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{
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if (!omap2_can_sleep()) {
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if (omap_irq_pending())
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return;
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omap2_enter_mpu_retention();
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return;
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}
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if (omap_irq_pending())
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return;
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omap2_enter_full_retention();
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}
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static void __init prcm_setup_regs(void)
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{
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int i, num_mem_banks;
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struct powerdomain *pwrdm;
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/*
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* Enable autoidle
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* XXX This should be handled by hwmod code or PRCM init code
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*/
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omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
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OMAP2_PRCM_SYSCONFIG_OFFSET);
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/*
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* Set CORE powerdomain memory banks to retain their contents
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* during RETENTION
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*/
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num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
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for (i = 0; i < num_mem_banks; i++)
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pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
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pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
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pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
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/* Force-power down DSP, GFX powerdomains */
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pwrdm = clkdm_get_pwrdm(dsp_clkdm);
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pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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pwrdm = clkdm_get_pwrdm(gfx_clkdm);
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pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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/* Enable hardware-supervised idle for all clkdms */
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clkdm_for_each(omap_pm_clkdms_setup, NULL);
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clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
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omap_common_suspend_init(omap2_enter_full_retention);
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/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
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* stabilisation */
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omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
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OMAP2_PRCM_CLKSSETUP_OFFSET);
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/* Configure automatic voltage transition */
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omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
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OMAP2_PRCM_VOLTSETUP_OFFSET);
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omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
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(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
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OMAP24XX_MEMRETCTRL_MASK |
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(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
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(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
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OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
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/* Enable wake-up events */
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omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
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WKUP_MOD, PM_WKEN);
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/* Enable SYS_CLKEN control when all domains idle */
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omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
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OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
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}
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int __init omap2_pm_init(void)
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{
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u32 l;
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printk(KERN_INFO "Power Management for OMAP2 initializing\n");
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l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
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printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
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/* Look up important powerdomains */
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mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
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if (!mpu_pwrdm)
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pr_err("PM: mpu_pwrdm not found\n");
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core_pwrdm = pwrdm_lookup("core_pwrdm");
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if (!core_pwrdm)
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pr_err("PM: core_pwrdm not found\n");
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/* Look up important clockdomains */
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mpu_clkdm = clkdm_lookup("mpu_clkdm");
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if (!mpu_clkdm)
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pr_err("PM: mpu_clkdm not found\n");
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wkup_clkdm = clkdm_lookup("wkup_clkdm");
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if (!wkup_clkdm)
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pr_err("PM: wkup_clkdm not found\n");
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dsp_clkdm = clkdm_lookup("dsp_clkdm");
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if (!dsp_clkdm)
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pr_err("PM: dsp_clkdm not found\n");
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gfx_clkdm = clkdm_lookup("gfx_clkdm");
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if (!gfx_clkdm)
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pr_err("PM: gfx_clkdm not found\n");
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osc_ck = clk_get(NULL, "osc_ck");
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if (IS_ERR(osc_ck)) {
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printk(KERN_ERR "could not get osc_ck\n");
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return -ENODEV;
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}
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if (cpu_is_omap242x()) {
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emul_ck = clk_get(NULL, "emul_ck");
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if (IS_ERR(emul_ck)) {
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printk(KERN_ERR "could not get emul_ck\n");
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clk_put(osc_ck);
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return -ENODEV;
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}
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}
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prcm_setup_regs();
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/*
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* We copy the assembler sleep/wakeup routines to SRAM.
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* These routines need to be in SRAM as that's the only
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* memory the MPU can see when it wakes up after the entire
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* chip enters idle.
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*/
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omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
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omap24xx_cpu_suspend_sz);
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arm_pm_idle = omap2_pm_idle;
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return 0;
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}
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