236 lines
6.8 KiB
C
236 lines
6.8 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/mach/irq.h>
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#include <asm/exception.h>
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#include "common.h"
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#include "hardware.h"
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#include "irq-common.h"
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#define AVIC_INTCNTL 0x00 /* int control reg */
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#define AVIC_NIMASK 0x04 /* int mask reg */
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#define AVIC_INTENNUM 0x08 /* int enable number reg */
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#define AVIC_INTDISNUM 0x0C /* int disable number reg */
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#define AVIC_INTENABLEH 0x10 /* int enable reg high */
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#define AVIC_INTENABLEL 0x14 /* int enable reg low */
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#define AVIC_INTTYPEH 0x18 /* int type reg high */
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#define AVIC_INTTYPEL 0x1C /* int type reg low */
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#define AVIC_NIPRIORITY(x) (0x20 + 4 * (7 - (x))) /* int priority */
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#define AVIC_NIVECSR 0x40 /* norm int vector/status */
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#define AVIC_FIVECSR 0x44 /* fast int vector/status */
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#define AVIC_INTSRCH 0x48 /* int source reg high */
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#define AVIC_INTSRCL 0x4C /* int source reg low */
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#define AVIC_INTFRCH 0x50 /* int force reg high */
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#define AVIC_INTFRCL 0x54 /* int force reg low */
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#define AVIC_NIPNDH 0x58 /* norm int pending high */
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#define AVIC_NIPNDL 0x5C /* norm int pending low */
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#define AVIC_FIPNDH 0x60 /* fast int pending high */
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#define AVIC_FIPNDL 0x64 /* fast int pending low */
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#define AVIC_NUM_IRQS 64
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/* low power interrupt mask registers */
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#define MX25_CCM_LPIMR0 0x68
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#define MX25_CCM_LPIMR1 0x6C
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static void __iomem *avic_base;
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static void __iomem *mx25_ccm_base;
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static struct irq_domain *domain;
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#ifdef CONFIG_FIQ
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static int avic_set_irq_fiq(unsigned int hwirq, unsigned int type)
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{
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unsigned int irqt;
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if (hwirq >= AVIC_NUM_IRQS)
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return -EINVAL;
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if (hwirq < AVIC_NUM_IRQS / 2) {
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irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq);
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imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL);
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} else {
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hwirq -= AVIC_NUM_IRQS / 2;
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irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq);
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imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH);
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}
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return 0;
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}
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#endif /* CONFIG_FIQ */
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static struct mxc_extra_irq avic_extra_irq = {
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#ifdef CONFIG_FIQ
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.set_irq_fiq = avic_set_irq_fiq,
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#endif
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};
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#ifdef CONFIG_PM
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static u32 avic_saved_mask_reg[2];
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static void avic_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = gc->chip_types;
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int idx = d->hwirq >> 5;
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avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);
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imx_writel(gc->wake_active, avic_base + ct->regs.mask);
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if (mx25_ccm_base) {
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u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
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MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
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/*
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* The interrupts which are still enabled will be used as wakeup
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* sources. Allow those interrupts in low-power mode.
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* The LPIMR registers use 0 to allow an interrupt, the AVIC
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* registers use 1.
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*/
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imx_writel(~gc->wake_active, mx25_ccm_base + offs);
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}
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}
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static void avic_irq_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = gc->chip_types;
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int idx = d->hwirq >> 5;
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imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
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if (mx25_ccm_base) {
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u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?
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MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;
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imx_writel(0xffffffff, mx25_ccm_base + offs);
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}
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}
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#else
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#define avic_irq_suspend NULL
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#define avic_irq_resume NULL
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#endif
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static __init void avic_init_gc(int idx, unsigned int irq_start)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
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handle_level_irq);
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gc->private = &avic_extra_irq;
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gc->wake_enabled = IRQ_MSK(32);
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_ack = irq_gc_mask_clr_bit;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.irq_suspend = avic_irq_suspend;
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ct->chip.irq_resume = avic_irq_resume;
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ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
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ct->regs.ack = ct->regs.mask;
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
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}
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static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
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{
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u32 nivector;
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do {
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nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16;
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if (nivector == 0xffff)
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break;
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handle_domain_irq(domain, nivector, regs);
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} while (1);
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}
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/*
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* This function initializes the AVIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* to the kernel for each interrupt source.
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*/
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void __init mxc_init_irq(void __iomem *irqbase)
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{
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struct device_node *np;
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int irq_base;
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int i;
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avic_base = irqbase;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
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mx25_ccm_base = of_iomap(np, 0);
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if (mx25_ccm_base) {
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/*
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* By default, we mask all interrupts. We set the actual mask
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* before we go into low-power mode.
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*/
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imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);
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imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);
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}
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/* put the AVIC into the reset value with
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* all interrupts disabled
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*/
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imx_writel(0, avic_base + AVIC_INTCNTL);
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imx_writel(0x1f, avic_base + AVIC_NIMASK);
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/* disable all interrupts */
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imx_writel(0, avic_base + AVIC_INTENABLEH);
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imx_writel(0, avic_base + AVIC_INTENABLEL);
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/* all IRQ no FIQ */
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imx_writel(0, avic_base + AVIC_INTTYPEH);
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imx_writel(0, avic_base + AVIC_INTTYPEL);
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irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
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WARN_ON(irq_base < 0);
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np = of_find_compatible_node(NULL, NULL, "fsl,avic");
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domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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WARN_ON(!domain);
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for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
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avic_init_gc(i, irq_base);
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/* Set default priority value (0) for all IRQ's */
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for (i = 0; i < 8; i++)
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imx_writel(0, avic_base + AVIC_NIPRIORITY(i));
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set_handle_irq(avic_handle_irq);
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#ifdef CONFIG_FIQ
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/* Initialize FIQ */
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init_FIQ(FIQ_START);
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#endif
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printk(KERN_INFO "MXC IRQ initialized\n");
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}
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