156 lines
4.5 KiB
C
156 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2014_T3.0"
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*/
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#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
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(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
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BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
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BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
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#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
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(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
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BIT(16) | BIT(17) | BIT(18)))
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#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
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#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
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#define DB_GP_88F68XX_GPP_POL_LOW 0x0
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#define DB_GP_88F68XX_GPP_POL_MID 0x0
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/* IO expander on Marvell GP board includes e.g. fan enabling */
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struct marvell_io_exp {
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u8 chip;
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u8 addr;
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u8 val;
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};
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static struct marvell_io_exp io_exp[] = {
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{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
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{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
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{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
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{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
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{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
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{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
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{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
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{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
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};
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static struct serdes_map board_serdes_map[] = {
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{PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct mv_ddr_topology_map board_topology_map = {
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1866L, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* memory_width */
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MV_DDR_DIE_CAP_4GBIT, /* mem_size */
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MV_DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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MV_DDR_TEMP_LOW, /* temperature */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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};
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x11244011, MVEBU_MPP_BASE + 0x08);
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writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
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writel(0x22200002, MVEBU_MPP_BASE + 0x10);
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writel(0x30042022, MVEBU_MPP_BASE + 0x14);
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writel(0x55550555, MVEBU_MPP_BASE + 0x18);
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writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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int i;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* Init I2C IO expanders */
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for (i = 0; i < ARRAY_SIZE(io_exp); i++)
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i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Marvell DB-88F6820-GP\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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