567 lines
14 KiB
C
Executable File
567 lines
14 KiB
C
Executable File
/*
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* Copyright (C) 2016 Novatek MicroElectronics Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/machine.h>
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#include <linux/iio/driver.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/thermal.h>
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#include <plat/adc_reg.h>
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#include <plat/efuse_protected.h>
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#include <plat/top.h>
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#define DRV_VERSION "1.03.000"
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#ifdef CONFIG_NVT_FPGA_EMULATION
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#define CALI_VDDADC 3300
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#else
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#define CALI_VDDADC 2700
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#endif
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#define CALI_OFFSET 0
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#define DEFAULT_THERMAL_LEVEL 259
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#define DEFAULT_THERMAL_528_LEVEL 231
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#define ADC_CHANNEL(num, id) \
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{ \
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.type = IIO_VOLTAGE, \
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.indexed = 1, \
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.channel = num, \
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.address = num, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
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.scan_index = num, \
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.scan_type = { \
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.sign = 's', \
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.realbits = 9, \
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.storagebits = 9, \
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.endianness = IIO_CPU, \
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}, \
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.datasheet_name = id, \
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}
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static uint nvt_adc_poll_mode = 1;
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module_param(nvt_adc_poll_mode, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(nvt_adc_poll_mode, "1:poll mode, 0:irq mode");
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static uint nvt_adc_pow2div = 1;
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module_param(nvt_adc_pow2div, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(nvt_adc_pow2div, "adc sample clock pow2 div");
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static uint nvt_adc_plusdiv = 0;
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module_param(nvt_adc_plusdiv, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(nvt_adc_plusdiv, "adc sample clock fine tune plus div");
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struct nvt_adc_state {
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u32 sample_rate;
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struct completion data_complete;
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u32 interrupt_status;
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u32 base;
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struct clk *clk;
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unsigned long trim_value;
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u32 cali_value;
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};
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static u32 adc_getreg(struct nvt_adc_state *adc, u32 offset)
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{
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return nvt_readl(adc->base + offset);
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}
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static void adc_setreg(struct nvt_adc_state *adc, u32 offset, u32 value)
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{
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nvt_writel(value, adc->base + offset);
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}
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static int adc_chk_enable(struct nvt_adc_state *adc)
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{
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union ADC_CTRL_REG ctrl_reg;
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ctrl_reg.reg = adc_getreg(adc, ADC_CTRL_REG_OFS);
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return ctrl_reg.bit.adc_en;
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}
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static void adc_set_enable(struct nvt_adc_state *adc, int input)
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{
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union ADC_CTRL_REG ctrl_reg;
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ctrl_reg.reg = adc_getreg(adc, ADC_CTRL_REG_OFS);
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ctrl_reg.bit.adc_en = input;
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adc_setreg(adc, ADC_CTRL_REG_OFS, ctrl_reg.reg);
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}
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static void adc_set_default_hw(struct nvt_adc_state *adc)
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{
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union ADC_CTRL_REG ctrl_reg;
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union ADC_INTCTRL_REG intctrl_reg;
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intctrl_reg.reg = 0xFF;
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adc_setreg(adc, ADC_INTCTRL_REG_OFS, intctrl_reg.reg);
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ctrl_reg.reg = adc_getreg(adc, ADC_CTRL_REG_OFS);
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ctrl_reg.bit.ain0_mode = 1;
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ctrl_reg.bit.ain1_mode = 1;
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ctrl_reg.bit.ain2_mode = 1;
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ctrl_reg.bit.ain3_mode = 1;
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ctrl_reg.bit.clkdiv = nvt_adc_pow2div;
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ctrl_reg.bit.sampavg = 0;
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ctrl_reg.bit.extsamp_cnt = nvt_adc_plusdiv;
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ctrl_reg.bit.adc_en = 0;
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adc_setreg(adc, ADC_CTRL_REG_OFS, ctrl_reg.reg);
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}
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static u32 nvt_adc_get_value(struct nvt_adc_state *adc, u8 channel)
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{
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u16 adc_data;
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adc_data = adc_getreg(adc, ADC_AIN0_DATA_REG_OFS + channel*4);
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return (adc_data+CALI_OFFSET)*adc->cali_value/511;
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}
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static int nvt_adc_read_raw(struct iio_dev *iio,
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struct iio_chan_spec const *channel, int *value,
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int *shift, long mask)
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{
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struct nvt_adc_state *adc = iio_priv(iio);
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if (!adc_chk_enable(adc))
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adc_set_enable(adc, 1);
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if(nvt_adc_poll_mode == 0)
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wait_for_completion(&adc->data_complete);
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*value = nvt_adc_get_value(adc, channel->address);
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return IIO_VAL_INT;
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case IIO_CHAN_INFO_SCALE:
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printk("IIO_CHAN_INFO_SCALE\n");
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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break;
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}
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return -EINVAL;
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}
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static irqreturn_t nvt_adc_irq(int irq, void *devid)
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{
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struct nvt_adc_state *adc = devid;
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adc->interrupt_status = adc_getreg(adc, ADC_STATUS_REG_OFS);
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if (adc->interrupt_status) {
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adc_setreg(adc, ADC_STATUS_REG_OFS, adc->interrupt_status);
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complete(&adc->data_complete);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static ssize_t nvt_adc_enable(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *iio = dev_to_iio_dev(dev);
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struct nvt_adc_state *adc = iio_priv(iio);
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unsigned long input;
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int ret;
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ret = kstrtoul(buf, 10, &input);
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if (ret < 0)
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return ret;
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adc_set_enable(adc, input);
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return len;
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}
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static ssize_t nvt_adc_is_enable(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *iio = dev_to_iio_dev(dev);
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struct nvt_adc_state *adc = iio_priv(iio);
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return sprintf(buf, "%d\n", adc_chk_enable(adc));
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}
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static ssize_t nvt_adc_get_poll_mode(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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return sprintf(buf, "%d\n", nvt_adc_poll_mode);
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}
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static u32 nvt_adc_set_frequency(struct nvt_adc_state *adc, u32 frequency)
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{
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int ret = 0;
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union ADC_CTRL_REG ctrl_reg;
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if (frequency > 38461) {
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pr_err("\nmax frequency is 38461 Hz, set value is %d\n", frequency);
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ret = -1;
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return ret;
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}
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ctrl_reg.reg = adc_getreg(adc, ADC_CTRL_REG_OFS);
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if (ctrl_reg.bit.adc_en) {
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pr_err("\nplease disable adc first\n");
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ret = -1;
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return ret;
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}
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nvt_adc_pow2div = ( clk_get_rate(adc->clk) / (frequency * 328));
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nvt_adc_plusdiv = ( (clk_get_rate(adc->clk) / (2 * (nvt_adc_pow2div + 1))) / (frequency * 4) - 26);
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adc->sample_rate = (clk_get_rate(adc->clk) / (2 * (nvt_adc_pow2div + 1))) / (4 * (26 + nvt_adc_plusdiv));
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pr_info("\nset frequency is %d\n", adc->sample_rate);
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ctrl_reg.bit.clkdiv = nvt_adc_pow2div;
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ctrl_reg.bit.extsamp_cnt = nvt_adc_plusdiv;
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adc_setreg(adc, ADC_CTRL_REG_OFS, ctrl_reg.reg);
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return ret;
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}
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static ssize_t nvt_adc_set_in_clk(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *iio = dev_to_iio_dev(dev);
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struct nvt_adc_state *adc = iio_priv(iio);
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unsigned long input;
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int ret;
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ret = kstrtoul(buf, 10, &input);
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if (ret < 0)
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return ret;
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nvt_adc_set_frequency(adc, input);
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return len;
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}
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static ssize_t nvt_adc_get_in_clk(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *iio = dev_to_iio_dev(dev);
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struct nvt_adc_state *adc = iio_priv(iio);
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return sprintf(buf, "%d\n", adc->sample_rate);
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}
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static const struct iio_chan_spec nvt_adc_channels[] = {
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IIO_CHAN_SOFT_TIMESTAMP(6),
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ADC_CHANNEL(0, "adc0"),
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ADC_CHANNEL(1, "adc1"),
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ADC_CHANNEL(2, "adc2"),
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};
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/* for consumer drivers */
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static struct iio_map nvt_adc_default_maps[] = {
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IIO_MAP("adc0", "nvt-adc0", "adc0"),
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IIO_MAP("adc1", "nvt-adc1", "adc1"),
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IIO_MAP("adc2", "nvt-adc2", "adc2"),
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{},
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};
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static IIO_DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, nvt_adc_is_enable, nvt_adc_enable, 0);
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static IIO_DEVICE_ATTR(poll_mode, S_IRUGO, nvt_adc_get_poll_mode, 0, 0);
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static IIO_DEVICE_ATTR(frequency, S_IRUGO | S_IWUSR, nvt_adc_get_in_clk, nvt_adc_set_in_clk, 0);
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static struct attribute *nvt_adc_attributes[] = {
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&iio_dev_attr_enable.dev_attr.attr,
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&iio_dev_attr_poll_mode.dev_attr.attr,
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&iio_dev_attr_frequency.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group nvt_attribute_group = {
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.attrs = nvt_adc_attributes,
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};
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static const struct iio_info nvt_adc_info = {
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.read_raw = &nvt_adc_read_raw,
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.attrs = &nvt_attribute_group,
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};
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static void thermal_get_trimdata(struct nvt_adc_state *adc)
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{
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u16 data = 0x0;
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if (efuse_readParamOps(EFUSE_THERMAL_TRIM_DATA, &data)) {
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if (nvt_get_chip_id() == CHIP_NA51055)
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adc->trim_value = DEFAULT_THERMAL_LEVEL;
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else
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adc->trim_value = DEFAULT_THERMAL_528_LEVEL;
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} else
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adc->trim_value = data;
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}
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static int thermal_get_temp(struct thermal_zone_device *thermal, int *temp)
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{
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struct nvt_adc_state *adc = thermal->devdata;
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union THERMAL_SENSOR_CONFIGURE_REG thermal_reg;
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union ADC_CTRL_REG ctrl_reg;
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signed long temp_value;
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ctrl_reg.reg = adc_getreg(adc, ADC_CTRL_REG_OFS);
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if (!ctrl_reg.bit.adc_en) {
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ctrl_reg.bit.adc_en = 1;
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adc_setreg(adc, ADC_CTRL_REG_OFS, ctrl_reg.reg);
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}
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thermal_reg.reg = adc_getreg(adc, THERMAL_SENSOR_CONFIGURE_REG_OFS);
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temp_value = thermal_reg.bit.ain_avg_out;
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if (nvt_get_chip_id() == CHIP_NA51055) {
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*temp = (temp_value - adc->trim_value)*13;
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*temp = *temp/10 + 30;
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} else {
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*temp = (temp_value - adc->trim_value)*1319;
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*temp = *temp/1000 + 30;
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}
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return 0;
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}
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static struct thermal_zone_device_ops ops = {
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.get_temp = thermal_get_temp,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id nvt_adc_of_dt_ids[] = {
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{ .compatible = "nvt,nvt_adc", },
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{},
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};
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MODULE_DEVICE_TABLE(of, nvt_adc_of_dt_ids);
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#endif
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#if (defined(CONFIG_NVT_IVOT_PLAT_NA51055) || defined(CONFIG_NVT_IVOT_PLAT_NA51089))
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static void nvt_adc_get_trimdata(struct nvt_adc_state *adc)
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{
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u16 data0, data1 = 0x0;
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u32 slope, cali_value = 0x0;
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u32 upper_bound = CALI_VDDADC + 200;
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u32 lower_bound = CALI_VDDADC - 200;
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#if (defined(CONFIG_NVT_IVOT_PLAT_NA51055))
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if (efuse_readParamOps(EFUSE_ADC_TRIM_A_DATA, &data0)) {
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adc->cali_value = CALI_VDDADC;
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} else {
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data0 = ((data0 & 0x3F80)>>7); //Trim A @ bit[13..7]
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if (efuse_readParamOps(EFUSE_ADC_TRIM_B_DATA, &data1) ) {
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adc->cali_value = CALI_VDDADC;
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} else {
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data1 = (data1 & 0x1FF); //Trim B @ bit[8..0]
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slope = data1 - data0;
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cali_value = (511 - data0) * 1000;
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cali_value = 2*(cali_value/slope) + 500;
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if ((cali_value > upper_bound) || (cali_value < lower_bound))
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adc->cali_value = CALI_VDDADC;
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else
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adc->cali_value = cali_value;
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}
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}
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#else //#if (defined(CONFIG_NVT_IVOT_PLAT_NA51089)
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if (efuse_readParamOps(EFUSE_ADC_TRAM_A_DATA, &data0)) {
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adc->cali_value = CALI_VDDADC;
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} else {
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if (efuse_readParamOps(EFUSE_ADC_TRAM_B_DATA, &data1)) {
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adc->cali_value = CALI_VDDADC;
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} else {
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slope = data1 - data0;
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cali_value = (511 - data0) * 1000;
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cali_value = 2*(cali_value/slope) + 500;
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if ((cali_value > upper_bound) || (cali_value < lower_bound))
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adc->cali_value = CALI_VDDADC;
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else
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adc->cali_value = cali_value;
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}
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}
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#endif
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}
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#endif
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static int nvt_adc_probe(struct platform_device *pdev)
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{
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struct iio_dev *iio;
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struct nvt_adc_state *adc;
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int err = 0, irq;
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struct resource *res;
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struct thermal_zone_device *thermal_zone = NULL;
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#ifdef CONFIG_OF
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const struct of_device_id *of_id;
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of_id = of_match_device(nvt_adc_of_dt_ids, &pdev->dev);
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if (!of_id) {
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dev_err(&pdev->dev, "[NVT ADC] OF not found\n");
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return -EINVAL;
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}
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//pr_info("%s %d: of_id->compatible = %s\n", __func__, __LINE__, of_id->compatible);
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#endif
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adc = kzalloc(sizeof(struct nvt_adc_state), GFP_KERNEL);
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if (!adc)
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return -ENOMEM;
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iio = iio_device_alloc(sizeof(*adc));
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if (!iio)
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return -ENOMEM;
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adc = iio_priv(iio);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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pr_err("%s: get IO resource fail\n", __func__);
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goto iio_free;
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}
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adc->base = (u32)devm_ioremap_resource(&pdev->dev, res);
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if (!adc->base)
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goto iio_free;
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adc->clk = clk_get(&pdev->dev, dev_name(&pdev->dev));
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if (!IS_ERR(adc->clk)) {
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clk_prepare(adc->clk);
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clk_enable(adc->clk);
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} else {
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pr_err("%s: %s clk not found\n", __func__, dev_name(&pdev->dev));
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goto iio_free;
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}
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if(nvt_adc_poll_mode == 0) {
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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pr_err("%s: get irq fail %d\n", __func__, irq);
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goto iio_free;
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}
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init_completion(&adc->data_complete);
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err = request_irq(irq, nvt_adc_irq, 0, pdev->name, adc);
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if (err < 0) {
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dev_err(&pdev->dev, "failed to request IRQ\n");
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goto iio_free;
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}
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|
}
|
|
|
|
#if (defined(CONFIG_NVT_IVOT_PLAT_NA51055) || defined(CONFIG_NVT_IVOT_PLAT_NA51089))
|
|
nvt_adc_get_trimdata(adc);
|
|
#else
|
|
if (of_property_read_u32(pdev->dev.of_node, "cali_value", &adc->cali_value))
|
|
adc->cali_value = CALI_VDDADC;
|
|
#endif
|
|
|
|
adc->sample_rate = (clk_get_rate(adc->clk) / (2 * (nvt_adc_pow2div + 1))) / (4 * (26 + nvt_adc_plusdiv));
|
|
|
|
adc_set_default_hw(adc);
|
|
|
|
iio->name = "nvt_adc";
|
|
iio->modes = INDIO_DIRECT_MODE;
|
|
iio->info = &nvt_adc_info;
|
|
iio->dev.parent = &pdev->dev;
|
|
iio->dev.of_node = pdev->dev.of_node;
|
|
iio->channels = (void *)&nvt_adc_channels;
|
|
iio->num_channels = sizeof(nvt_adc_channels)/sizeof(nvt_adc_channels[0]);
|
|
err = iio_map_array_register(iio, nvt_adc_default_maps);
|
|
if (err < 0)
|
|
goto iio_free;
|
|
|
|
err = iio_device_register(iio);
|
|
if(err)
|
|
goto iio_free;
|
|
|
|
pr_info("%s: %s done voltage %d ver %s\n", __func__, dev_name(&pdev->dev), adc->cali_value, DRV_VERSION);
|
|
|
|
|
|
thermal_zone = thermal_zone_device_register("nvt_thermal", 0, 0,
|
|
adc, &ops, NULL, 0, 0);
|
|
if (IS_ERR(thermal_zone)) {
|
|
dev_err(&pdev->dev, "thermal zone device is NULL\n");
|
|
return PTR_ERR(thermal_zone);
|
|
}
|
|
|
|
thermal_get_trimdata(adc);
|
|
|
|
dev_info(&thermal_zone->device, "Thermal Sensor probe\n");
|
|
|
|
platform_set_drvdata(pdev, thermal_zone);
|
|
|
|
return 0;
|
|
|
|
iio_free:
|
|
iio_device_free(iio);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int nvt_adc_remove(struct platform_device *pdev)
|
|
{
|
|
struct iio_dev *iio = platform_get_drvdata(pdev);;
|
|
|
|
iio_device_unregister(iio);
|
|
iio_device_free(iio);
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static struct platform_driver nvt_adc_driver = {
|
|
.driver = {
|
|
.name = "nvt_adc",
|
|
.owner = THIS_MODULE,
|
|
#ifdef CONFIG_OF
|
|
.of_match_table = nvt_adc_of_dt_ids,
|
|
#endif
|
|
},
|
|
.probe = nvt_adc_probe,
|
|
.remove = nvt_adc_remove,
|
|
};
|
|
|
|
static int __init nvt_adc_init_driver(void)
|
|
{
|
|
return platform_driver_register(&nvt_adc_driver);
|
|
}
|
|
module_init(nvt_adc_init_driver);
|
|
|
|
static void __exit nvt_adc_exit_driver(void)
|
|
{
|
|
platform_driver_unregister(&nvt_adc_driver);
|
|
}
|
|
module_exit(nvt_adc_exit_driver);
|
|
|
|
MODULE_AUTHOR("Novatek");
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_DESCRIPTION("NVT ADC driver");
|
|
MODULE_LICENSE("GPL v2");
|