126 lines
4.1 KiB
C
126 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015, Linaro Limited
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*/
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#ifndef __LINUX_ARM_SMCCC_H
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#define __LINUX_ARM_SMCCC_H
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/*
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* This file provides common defines for ARM SMC Calling Convention as
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* specified in
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* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
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*/
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#define ARM_SMCCC_STD_CALL 0
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#define ARM_SMCCC_FAST_CALL 1
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#define ARM_SMCCC_TYPE_SHIFT 31
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#define ARM_SMCCC_SMC_32 0
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#define ARM_SMCCC_SMC_64 1
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#define ARM_SMCCC_CALL_CONV_SHIFT 30
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#define ARM_SMCCC_OWNER_MASK 0x3F
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#define ARM_SMCCC_OWNER_SHIFT 24
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#define ARM_SMCCC_FUNC_MASK 0xFFFF
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#define ARM_SMCCC_IS_FAST_CALL(smc_val) \
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((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT))
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#define ARM_SMCCC_IS_64(smc_val) \
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((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT))
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#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val) & ARM_SMCCC_FUNC_MASK)
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#define ARM_SMCCC_OWNER_NUM(smc_val) \
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(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK)
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#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \
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(((type) << ARM_SMCCC_TYPE_SHIFT) | \
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((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \
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(((owner) & ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \
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((func_num) & ARM_SMCCC_FUNC_MASK))
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#define ARM_SMCCC_OWNER_ARCH 0
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#define ARM_SMCCC_OWNER_CPU 1
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#define ARM_SMCCC_OWNER_SIP 2
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#define ARM_SMCCC_OWNER_OEM 3
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#define ARM_SMCCC_OWNER_STANDARD 4
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#define ARM_SMCCC_OWNER_TRUSTED_APP 48
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#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49
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#define ARM_SMCCC_OWNER_TRUSTED_OS 50
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#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63
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#define ARM_SMCCC_QUIRK_NONE 0
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#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */
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#ifndef __ASSEMBLY__
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#include <linux/linkage.h>
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#include <linux/types.h>
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/**
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* struct arm_smccc_res - Result from SMC/HVC call
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* @a0-a3 result values from registers 0 to 3
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*/
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struct arm_smccc_res {
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unsigned long a0;
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unsigned long a1;
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unsigned long a2;
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unsigned long a3;
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};
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/**
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* struct arm_smccc_quirk - Contains quirk information
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* @id: quirk identification
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* @state: quirk specific information
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* @a6: Qualcomm quirk entry for returning post-smc call contents of a6
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*/
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struct arm_smccc_quirk {
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int id;
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union {
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unsigned long a6;
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} state;
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};
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/**
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* __arm_smccc_smc() - make SMC calls
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* @a0-a7: arguments passed in registers 0 to 7
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* @res: result values from registers 0 to 3
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* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
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*
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* This function is used to make SMC calls following SMC Calling Convention.
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* The content of the supplied param are copied to registers 0 to 7 prior
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* to the SMC instruction. The return values are updated with the content
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* from register 0 to 3 on return from the SMC instruction. An optional
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* quirk structure provides vendor specific behavior.
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*/
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asmlinkage void __arm_smccc_smc(unsigned long a0, unsigned long a1,
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unsigned long a2, unsigned long a3, unsigned long a4,
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unsigned long a5, unsigned long a6, unsigned long a7,
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struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
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/**
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* __arm_smccc_hvc() - make HVC calls
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* @a0-a7: arguments passed in registers 0 to 7
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* @res: result values from registers 0 to 3
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* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required.
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*
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* This function is used to make HVC calls following SMC Calling
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* Convention. The content of the supplied param are copied to registers 0
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* to 7 prior to the HVC instruction. The return values are updated with
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* the content from register 0 to 3 on return from the HVC instruction. An
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* optional quirk structure provides vendor specific behavior.
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*/
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asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
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unsigned long a2, unsigned long a3, unsigned long a4,
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unsigned long a5, unsigned long a6, unsigned long a7,
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struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
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#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
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#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
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#define arm_smccc_hvc(...) __arm_smccc_hvc(__VA_ARGS__, NULL)
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#define arm_smccc_hvc_quirk(...) __arm_smccc_hvc(__VA_ARGS__)
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#endif /*__ASSEMBLY__*/
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#endif /*__LINUX_ARM_SMCCC_H*/
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