269 lines
6.8 KiB
C
269 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cadence WDT driver - Used by Xilinx Zynq
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* Reference: Linux kernel Cadence watchdog driver.
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*
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* Author(s): Shreenidhi Shedi <yesshedi@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <clk.h>
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#include <linux/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct cdns_regs {
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u32 zmr; /* WD Zero mode register, offset - 0x0 */
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u32 ccr; /* Counter Control Register offset - 0x4 */
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u32 restart; /* Restart key register, offset - 0x8 */
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u32 status; /* Status Register, offset - 0xC */
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};
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struct cdns_wdt_priv {
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bool rst;
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u32 timeout;
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struct cdns_regs *regs;
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};
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#define CDNS_WDT_DEFAULT_TIMEOUT 10
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/* Supports 1 - 516 sec */
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#define CDNS_WDT_MIN_TIMEOUT 1
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#define CDNS_WDT_MAX_TIMEOUT 516
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/* Restart key */
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#define CDNS_WDT_RESTART_KEY 0x00001999
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/* Counter register access key */
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#define CDNS_WDT_REGISTER_ACCESS_KEY 0x00920000
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/* Counter value divisor */
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#define CDNS_WDT_COUNTER_VALUE_DIVISOR 0x1000
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/* Clock prescaler value and selection */
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#define CDNS_WDT_PRESCALE_64 64
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#define CDNS_WDT_PRESCALE_512 512
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#define CDNS_WDT_PRESCALE_4096 4096
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#define CDNS_WDT_PRESCALE_SELECT_64 1
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#define CDNS_WDT_PRESCALE_SELECT_512 2
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#define CDNS_WDT_PRESCALE_SELECT_4096 3
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/* Input clock frequency */
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#define CDNS_WDT_CLK_75MHZ 75000000
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/* Counter maximum value */
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#define CDNS_WDT_COUNTER_MAX 0xFFF
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/********************* Register Map **********************************/
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/*
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* Zero Mode Register - This register controls how the time out is indicated
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* and also contains the access code to allow writes to the register (0xABC).
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*/
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#define CDNS_WDT_ZMR_WDEN_MASK 0x00000001 /* Enable the WDT */
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#define CDNS_WDT_ZMR_RSTEN_MASK 0x00000002 /* Enable the reset output */
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#define CDNS_WDT_ZMR_IRQEN_MASK 0x00000004 /* Enable IRQ output */
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#define CDNS_WDT_ZMR_RSTLEN_16 0x00000030 /* Reset pulse of 16 pclk cycles */
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#define CDNS_WDT_ZMR_ZKEY_VAL 0x00ABC000 /* Access key, 0xABC << 12 */
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/*
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* Counter Control register - This register controls how fast the timer runs
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* and the reset value and also contains the access code to allow writes to
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* the register.
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*/
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#define CDNS_WDT_CCR_CRV_MASK 0x00003FFC /* Counter reset value */
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/* Write access to Registers */
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static inline void cdns_wdt_writereg(u32 *addr, u32 val)
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{
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writel(val, addr);
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}
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/**
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* cdns_wdt_reset - Reload the watchdog timer (i.e. pat the watchdog).
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*
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* @dev: Watchdog device
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*
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* Write the restart key value (0x00001999) to the restart register.
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*
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* Return: Always 0
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*/
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static int cdns_wdt_reset(struct udevice *dev)
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{
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struct cdns_wdt_priv *priv = dev_get_priv(dev);
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debug("%s\n", __func__);
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cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
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return 0;
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}
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/**
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* cdns_wdt_start - Enable and start the watchdog.
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*
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* @dev: Watchdog device
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* @timeout: Timeout value
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* @flags: Driver flags
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*
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* The counter value is calculated according to the formula:
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* count = (timeout * clock) / prescaler + 1.
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*
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* The calculated count is divided by 0x1000 to obtain the field value
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* to write to counter control register.
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*
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* Clears the contents of prescaler and counter reset value. Sets the
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* prescaler to 4096 and the calculated count and access key
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* to write to CCR Register.
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*
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* Sets the WDT (WDEN bit) and either the Reset signal(RSTEN bit)
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* or Interrupt signal(IRQEN) with a specified cycles and the access
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* key to write to ZMR Register.
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*
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* Return: Upon success 0, failure -1.
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*/
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static int cdns_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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ulong clk_f;
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u32 count, prescaler, ctrl_clksel, data = 0;
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struct clk clock;
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struct cdns_wdt_priv *priv = dev_get_priv(dev);
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if (clk_get_by_index(dev, 0, &clock) < 0) {
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dev_err(dev, "failed to get clock\n");
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return -1;
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}
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clk_f = clk_get_rate(&clock);
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if (IS_ERR_VALUE(clk_f)) {
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dev_err(dev, "failed to get rate\n");
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return -1;
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}
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if ((timeout < CDNS_WDT_MIN_TIMEOUT) ||
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(timeout > CDNS_WDT_MAX_TIMEOUT)) {
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timeout = priv->timeout;
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}
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debug("%s: CLK_FREQ %ld, timeout %lld\n", __func__, clk_f, timeout);
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if (clk_f <= CDNS_WDT_CLK_75MHZ) {
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prescaler = CDNS_WDT_PRESCALE_512;
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ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_512;
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} else {
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prescaler = CDNS_WDT_PRESCALE_4096;
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ctrl_clksel = CDNS_WDT_PRESCALE_SELECT_4096;
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}
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/*
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* Counter value divisor to obtain the value of
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* counter reset to be written to control register.
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*/
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count = (timeout * (clk_f / prescaler)) /
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CDNS_WDT_COUNTER_VALUE_DIVISOR + 1;
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if (count > CDNS_WDT_COUNTER_MAX)
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count = CDNS_WDT_COUNTER_MAX;
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cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL);
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count = (count << 2) & CDNS_WDT_CCR_CRV_MASK;
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/* Write counter access key first to be able write to register */
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data = count | CDNS_WDT_REGISTER_ACCESS_KEY | ctrl_clksel;
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cdns_wdt_writereg(&priv->regs->ccr, data);
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data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTLEN_16 |
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CDNS_WDT_ZMR_ZKEY_VAL;
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/* Reset on timeout if specified in device tree. */
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if (priv->rst) {
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data |= CDNS_WDT_ZMR_RSTEN_MASK;
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data &= ~CDNS_WDT_ZMR_IRQEN_MASK;
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} else {
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data &= ~CDNS_WDT_ZMR_RSTEN_MASK;
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data |= CDNS_WDT_ZMR_IRQEN_MASK;
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}
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cdns_wdt_writereg(&priv->regs->zmr, data);
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cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY);
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return 0;
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}
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/**
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* cdns_wdt_stop - Stop the watchdog.
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*
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* @dev: Watchdog device
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*
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* Read the contents of the ZMR register, clear the WDEN bit in the register
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* and set the access key for successful write.
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*
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* Return: Always 0
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*/
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static int cdns_wdt_stop(struct udevice *dev)
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{
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struct cdns_wdt_priv *priv = dev_get_priv(dev);
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cdns_wdt_writereg(&priv->regs->zmr,
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CDNS_WDT_ZMR_ZKEY_VAL & (~CDNS_WDT_ZMR_WDEN_MASK));
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return 0;
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}
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/**
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* cdns_wdt_probe - Probe call for the device.
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*
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* @dev: Handle to the udevice structure.
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*
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* Return: Always 0.
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*/
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static int cdns_wdt_probe(struct udevice *dev)
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{
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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return 0;
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}
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static int cdns_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct cdns_wdt_priv *priv = dev_get_priv(dev);
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priv->regs = (struct cdns_regs *)dev_read_addr(dev);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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priv->timeout = dev_read_u32_default(dev, "timeout-sec",
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CDNS_WDT_DEFAULT_TIMEOUT);
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priv->rst = dev_read_bool(dev, "reset-on-timeout");
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debug("%s: timeout %d, reset %d\n", __func__, priv->timeout, priv->rst);
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return 0;
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}
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static const struct wdt_ops cdns_wdt_ops = {
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.start = cdns_wdt_start,
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.reset = cdns_wdt_reset,
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.stop = cdns_wdt_stop,
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/* There is no bit/reg/support in IP for expire_now functionality */
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};
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static const struct udevice_id cdns_wdt_ids[] = {
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{ .compatible = "cdns,wdt-r1p2" },
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{}
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};
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U_BOOT_DRIVER(cdns_wdt) = {
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.name = "cdns_wdt",
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.id = UCLASS_WDT,
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.of_match = cdns_wdt_ids,
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.probe = cdns_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct cdns_wdt_priv),
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.ofdata_to_platdata = cdns_wdt_ofdata_to_platdata,
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.ops = &cdns_wdt_ops,
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};
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