147 lines
6.0 KiB
C
Executable File
147 lines
6.0 KiB
C
Executable File
/**
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NVT hardware description
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To define NVT platform IO address
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@file hardware.h
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_PLAT_HARDWARE_H
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#define __ASM_ARCH_PLAT_HARDWARE_H
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/*
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* ----------------------------------------------------------------------------
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* Interrupts (GIC)
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* ----------------------------------------------------------------------------
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*/
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#define NVT_GIC_DIST_PHYS_BASE (0xf9c01000)
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#define NVT_GIC_CPU_PHYS_BASE (0xf9c02000)
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//#define NVT_CPU_REG_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x1400000)
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//#define NVT_CPU_REG_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x1400000)
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/*
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* ----------------------------------------------------------------------------
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* Peripheral mapping address
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* ----------------------------------------------------------------------------
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*/
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#define NVT_PERIPHERAL_PHYS_BASE (0xFE000000)
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#define NVT_PERIPHERAL_VIRT_BASE IOMEM(0xFE300000)
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#define NVT_PERIPHERAL_SIZE 0xD00000
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#define NVT_TOP_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0030000)
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#define NVT_TOP_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0030000)
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#define NVT_CG_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0000000)
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#define NVT_CG_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0000000)
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#define NVT_PAD_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0040000)
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#define NVT_PAD_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0040000)
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#define NVT_TIMER_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0040000)
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#define NVT_TIMER_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0040000)
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#define NVT_GPIO_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0070000)
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#define NVT_GPIO_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0070000)
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#define NVT_RTC_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0090000)
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#define NVT_RTC_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0090000)
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#define NVT_I2C1_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0220000)
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#define NVT_I2C1_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0220000)
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#define NVT_I2C2_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0350000)
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#define NVT_I2C2_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0350000)
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#define NVT_I2C3_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x03A0000)
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#define NVT_I2C3_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x03A0000)
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#define NVT_I2C4_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x03B0000)
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#define NVT_I2C4_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x03B0000)
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#define NVT_I2C5_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x03C0000)
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#define NVT_I2C5_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x03C0000)
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#define NVT_I2C6_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x03D0000)
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#define NVT_I2C6_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x03D0000)
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#define NVT_I2C7_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x03E0000)
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#define NVT_I2C7_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x03E0000)
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#define NVT_SPI1_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0230000)
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#define NVT_SPI1_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0230000)
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#define NVT_SPI2_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0320000)
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#define NVT_SPI2_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0320000)
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#define NVT_SPI3_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0340000)
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#define NVT_SPI3_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0340000)
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#define NVT_SPI4_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0360000)
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#define NVT_SPI4_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0360000)
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#define NVT_SPI5_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0390000)
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#define NVT_SPI5_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0390000)
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#define NVT_UART1_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0200000)
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#define NVT_UART1_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0200000)
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#define NVT_UART2_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0220000)
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#define NVT_UART2_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0220000)
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#define NVT_UART3_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0240000)
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#define NVT_UART3_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0240000)
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#define NVT_UART4_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0260000)
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#define NVT_UART4_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0260000)
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#define NVT_USB1_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0600000)
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#define NVT_USB1_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0600000)
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#define NVT_USB3_CTRL_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x0670000)
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#define NVT_USB3_CTRL_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x0670000)
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#define NVT_USB3_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x1700000)
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#define NVT_USB3_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x1700000)
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#define NVT_CC_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x00090000)
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#define NVT_CC_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x00090000)
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#define NVT_WDT_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x008A0000)
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#define NVT_WDT_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x008A0000)
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#define NVT_PWM_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x00210000)
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#define NVT_PWM_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x00210000)
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#define NVT_TGE_BASE_PHYS (NVT_PERIPHERAL_PHYS_BASE + 0x00CC0000)
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#define NVT_TGE_BASE_VIRT (NVT_PERIPHERAL_VIRT_BASE + 0x00CC0000)
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#define NVT_PERIPHERAL_1_PHYS_BASE (0xFA000000)
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#define NVT_PERIPHERAL_1_VIRT_BASE IOMEM(0xFA000000)
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#define NVT_PERIPHERAL_1_SIZE 0xA00000
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#define NVT_DMA_BASE_PHYS (NVT_PERIPHERAL_1_PHYS_BASE + 0x0100000)
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#define NVT_DMA_BASE_VIRT (NVT_PERIPHERAL_1_VIRT_BASE + 0x0100000)
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#define NVT_SDIO1_BASE_PHYS (NVT_PERIPHERAL_1_PHYS_BASE + 0x0600000)
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#define NVT_SDIO1_BASE_VIRT (NVT_PERIPHERAL_1_VIRT_BASE + 0x0600000)
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#define NVT_NAND_BASE_PHYS (NVT_PERIPHERAL_1_PHYS_BASE + 0x0900000)
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#define NVT_NAND_BASE_VIRT (NVT_PERIPHERAL_1_VIRT_BASE + 0x0900000)
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#define NVT_PERIPHERAL_2_PHYS_BASE (0xFC000000)
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#define NVT_PERIPHERAL_2_VIRT_BASE IOMEM(0xFC000000)
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#define NVT_PERIPHERAL_2_SIZE 0xD00000
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#define NVT_XDMA_BASE_PHYS (NVT_PERIPHERAL_2_PHYS_BASE + 0x0A00000)
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#define NVT_XDMA_BASE_VIRT (NVT_PERIPHERAL_2_VIRT_BASE + 0x0A00000)
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#define NVT_ETH_BASE_PHYS (NVT_PERIPHERAL_2_PHYS_BASE + 0x0C00000)
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#define NVT_ETH_BASE_VIRT (NVT_PERIPHERAL_2_VIRT_BASE + 0x0C00000)
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#endif /* __ASM_ARCH_PLAT_HARDWARE_H */
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