581 lines
14 KiB
C
581 lines
14 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (c) BayLibre, SAS.
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* Author : Neil Armstrong <narmstrong@baylibre.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk-provider.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,lcc-mdm9615.h>
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#include "common.h"
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#include "clk-regmap.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-branch.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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static struct clk_pll pll4 = {
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.l_reg = 0x4,
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.m_reg = 0x8,
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.n_reg = 0xc,
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.config_reg = 0x14,
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.mode_reg = 0x0,
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.status_reg = 0x18,
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll4",
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.parent_names = (const char *[]){ "cxo" },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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};
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enum {
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P_CXO,
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P_PLL4,
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};
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static const struct parent_map lcc_cxo_pll4_map[] = {
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{ P_CXO, 0 },
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{ P_PLL4, 2 }
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};
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static const char * const lcc_cxo_pll4[] = {
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"cxo",
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"pll4_vote",
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};
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static struct freq_tbl clk_tbl_aif_osr_492[] = {
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{ 512000, P_PLL4, 4, 1, 240 },
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{ 768000, P_PLL4, 4, 1, 160 },
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{ 1024000, P_PLL4, 4, 1, 120 },
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{ 1536000, P_PLL4, 4, 1, 80 },
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{ 2048000, P_PLL4, 4, 1, 60 },
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{ 3072000, P_PLL4, 4, 1, 40 },
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{ 4096000, P_PLL4, 4, 1, 30 },
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{ 6144000, P_PLL4, 4, 1, 20 },
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{ 8192000, P_PLL4, 4, 1, 15 },
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{ 12288000, P_PLL4, 4, 1, 10 },
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{ 24576000, P_PLL4, 4, 1, 5 },
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{ 27000000, P_CXO, 1, 0, 0 },
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{ }
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};
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static struct freq_tbl clk_tbl_aif_osr_393[] = {
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{ 512000, P_PLL4, 4, 1, 192 },
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{ 768000, P_PLL4, 4, 1, 128 },
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 1536000, P_PLL4, 4, 1, 64 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ 3072000, P_PLL4, 4, 1, 32 },
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{ 4096000, P_PLL4, 4, 1, 24 },
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{ 6144000, P_PLL4, 4, 1, 16 },
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{ 8192000, P_PLL4, 4, 1, 12 },
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{ 12288000, P_PLL4, 4, 1, 8 },
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{ 24576000, P_PLL4, 4, 1, 4 },
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{ 27000000, P_CXO, 1, 0, 0 },
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{ }
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};
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static struct clk_rcg mi2s_osr_src = {
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.ns_reg = 0x48,
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.md_reg = 0x4c,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 24,
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.m_val_shift = 8,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_cxo_pll4_map,
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},
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.freq_tbl = clk_tbl_aif_osr_393,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_src",
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.parent_names = lcc_cxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static const char * const lcc_mi2s_parents[] = {
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"mi2s_osr_src",
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};
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static struct clk_branch mi2s_osr_clk = {
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.halt_reg = 0x50,
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.halt_bit = 1,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_div mi2s_div_clk = {
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.reg = 0x48,
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.shift = 10,
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.width = 4,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_div_clk",
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.parent_names = lcc_mi2s_parents,
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_branch mi2s_bit_div_clk = {
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.halt_reg = 0x50,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x48,
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_div_clk",
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.parent_names = (const char *[]){ "mi2s_div_clk" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux mi2s_bit_clk = {
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.reg = 0x48,
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.shift = 14,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_clk",
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.parent_names = (const char *[]){
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"mi2s_bit_div_clk",
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"mi2s_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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#define CLK_AIF_OSR_DIV(prefix, _ns, _md, hr) \
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static struct clk_rcg prefix##_osr_src = { \
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.ns_reg = _ns, \
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.md_reg = _md, \
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.mn = { \
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.mnctr_en_bit = 8, \
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.mnctr_reset_bit = 7, \
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.mnctr_mode_shift = 5, \
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.n_val_shift = 24, \
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.m_val_shift = 8, \
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.width = 8, \
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}, \
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.p = { \
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.pre_div_shift = 3, \
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.pre_div_width = 2, \
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}, \
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.s = { \
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.src_sel_shift = 0, \
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.parent_map = lcc_cxo_pll4_map, \
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}, \
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.freq_tbl = clk_tbl_aif_osr_393, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(9), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_src", \
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.parent_names = lcc_cxo_pll4, \
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.num_parents = 2, \
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.ops = &clk_rcg_ops, \
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.flags = CLK_SET_RATE_GATE, \
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}, \
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}, \
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}; \
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\
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static const char * const lcc_##prefix##_parents[] = { \
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#prefix "_osr_src", \
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}; \
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\
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static struct clk_branch prefix##_osr_clk = { \
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.halt_reg = hr, \
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.halt_bit = 1, \
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.halt_check = BRANCH_HALT_ENABLE, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(21), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_osr_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}; \
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\
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static struct clk_regmap_div prefix##_div_clk = { \
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.reg = _ns, \
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.shift = 10, \
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.width = 8, \
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_div_clk", \
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.parent_names = lcc_##prefix##_parents, \
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.num_parents = 1, \
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.ops = &clk_regmap_div_ops, \
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}, \
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}, \
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}; \
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\
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static struct clk_branch prefix##_bit_div_clk = { \
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.halt_reg = hr, \
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.halt_bit = 0, \
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.halt_check = BRANCH_HALT_ENABLE, \
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.clkr = { \
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.enable_reg = _ns, \
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.enable_mask = BIT(19), \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_div_clk", \
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.parent_names = (const char *[]){ \
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#prefix "_div_clk" \
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}, \
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.num_parents = 1, \
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.ops = &clk_branch_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}; \
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\
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static struct clk_regmap_mux prefix##_bit_clk = { \
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.reg = _ns, \
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.shift = 18, \
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.width = 1, \
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.clkr = { \
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.hw.init = &(struct clk_init_data){ \
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.name = #prefix "_bit_clk", \
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.parent_names = (const char *[]){ \
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#prefix "_bit_div_clk", \
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#prefix "_codec_clk", \
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}, \
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.num_parents = 2, \
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.ops = &clk_regmap_mux_closest_ops, \
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.flags = CLK_SET_RATE_PARENT, \
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}, \
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}, \
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}
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CLK_AIF_OSR_DIV(codec_i2s_mic, 0x60, 0x64, 0x68);
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CLK_AIF_OSR_DIV(spare_i2s_mic, 0x78, 0x7c, 0x80);
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CLK_AIF_OSR_DIV(codec_i2s_spkr, 0x6c, 0x70, 0x74);
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CLK_AIF_OSR_DIV(spare_i2s_spkr, 0x84, 0x88, 0x8c);
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static struct freq_tbl clk_tbl_pcm_492[] = {
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{ 256000, P_PLL4, 4, 1, 480 },
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{ 512000, P_PLL4, 4, 1, 240 },
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{ 768000, P_PLL4, 4, 1, 160 },
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{ 1024000, P_PLL4, 4, 1, 120 },
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{ 1536000, P_PLL4, 4, 1, 80 },
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{ 2048000, P_PLL4, 4, 1, 60 },
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{ 3072000, P_PLL4, 4, 1, 40 },
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{ 4096000, P_PLL4, 4, 1, 30 },
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{ 6144000, P_PLL4, 4, 1, 20 },
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{ 8192000, P_PLL4, 4, 1, 15 },
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{ 12288000, P_PLL4, 4, 1, 10 },
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{ 24576000, P_PLL4, 4, 1, 5 },
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{ 27000000, P_CXO, 1, 0, 0 },
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{ }
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};
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static struct freq_tbl clk_tbl_pcm_393[] = {
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{ 256000, P_PLL4, 4, 1, 384 },
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{ 512000, P_PLL4, 4, 1, 192 },
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{ 768000, P_PLL4, 4, 1, 128 },
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{ 1024000, P_PLL4, 4, 1, 96 },
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{ 1536000, P_PLL4, 4, 1, 64 },
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{ 2048000, P_PLL4, 4, 1, 48 },
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{ 3072000, P_PLL4, 4, 1, 32 },
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{ 4096000, P_PLL4, 4, 1, 24 },
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{ 6144000, P_PLL4, 4, 1, 16 },
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{ 8192000, P_PLL4, 4, 1, 12 },
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{ 12288000, P_PLL4, 4, 1, 8 },
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{ 24576000, P_PLL4, 4, 1, 4 },
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{ 27000000, P_CXO, 1, 0, 0 },
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{ }
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};
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static struct clk_rcg pcm_src = {
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.ns_reg = 0x54,
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.md_reg = 0x58,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 16,
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.m_val_shift = 16,
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.width = 16,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_cxo_pll4_map,
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},
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.freq_tbl = clk_tbl_pcm_393,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_src",
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.parent_names = lcc_cxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static struct clk_branch pcm_clk_out = {
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.halt_reg = 0x5c,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0x54,
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk_out",
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.parent_names = (const char *[]){ "pcm_src" },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_regmap_mux pcm_clk = {
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.reg = 0x54,
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.shift = 10,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk",
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.parent_names = (const char *[]){
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"pcm_clk_out",
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"pcm_codec_clk",
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},
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.num_parents = 2,
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_rcg slimbus_src = {
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.ns_reg = 0xcc,
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.md_reg = 0xd0,
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.mn = {
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.mnctr_en_bit = 8,
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.mnctr_reset_bit = 7,
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.mnctr_mode_shift = 5,
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.n_val_shift = 24,
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.m_val_shift = 8,
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.width = 8,
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},
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.p = {
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.pre_div_shift = 3,
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.pre_div_width = 2,
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},
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.s = {
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.src_sel_shift = 0,
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.parent_map = lcc_cxo_pll4_map,
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},
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.freq_tbl = clk_tbl_aif_osr_393,
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.clkr = {
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.enable_reg = 0xcc,
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "slimbus_src",
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.parent_names = lcc_cxo_pll4,
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.num_parents = 2,
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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static const char * const lcc_slimbus_parents[] = {
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"slimbus_src",
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};
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static struct clk_branch audio_slimbus_clk = {
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.halt_reg = 0xd4,
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.halt_bit = 0,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0xcc,
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.enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "audio_slimbus_clk",
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.parent_names = lcc_slimbus_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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static struct clk_branch sps_slimbus_clk = {
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.halt_reg = 0xd4,
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.halt_bit = 1,
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.halt_check = BRANCH_HALT_ENABLE,
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.clkr = {
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.enable_reg = 0xcc,
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "sps_slimbus_clk",
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.parent_names = lcc_slimbus_parents,
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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},
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};
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|
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static struct clk_regmap *lcc_mdm9615_clks[] = {
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[PLL4] = &pll4.clkr,
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[MI2S_OSR_SRC] = &mi2s_osr_src.clkr,
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[MI2S_OSR_CLK] = &mi2s_osr_clk.clkr,
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[MI2S_DIV_CLK] = &mi2s_div_clk.clkr,
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[MI2S_BIT_DIV_CLK] = &mi2s_bit_div_clk.clkr,
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[MI2S_BIT_CLK] = &mi2s_bit_clk.clkr,
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[PCM_SRC] = &pcm_src.clkr,
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[PCM_CLK_OUT] = &pcm_clk_out.clkr,
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[PCM_CLK] = &pcm_clk.clkr,
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[SLIMBUS_SRC] = &slimbus_src.clkr,
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[AUDIO_SLIMBUS_CLK] = &audio_slimbus_clk.clkr,
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[SPS_SLIMBUS_CLK] = &sps_slimbus_clk.clkr,
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[CODEC_I2S_MIC_OSR_SRC] = &codec_i2s_mic_osr_src.clkr,
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[CODEC_I2S_MIC_OSR_CLK] = &codec_i2s_mic_osr_clk.clkr,
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[CODEC_I2S_MIC_DIV_CLK] = &codec_i2s_mic_div_clk.clkr,
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[CODEC_I2S_MIC_BIT_DIV_CLK] = &codec_i2s_mic_bit_div_clk.clkr,
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[CODEC_I2S_MIC_BIT_CLK] = &codec_i2s_mic_bit_clk.clkr,
|
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[SPARE_I2S_MIC_OSR_SRC] = &spare_i2s_mic_osr_src.clkr,
|
|
[SPARE_I2S_MIC_OSR_CLK] = &spare_i2s_mic_osr_clk.clkr,
|
|
[SPARE_I2S_MIC_DIV_CLK] = &spare_i2s_mic_div_clk.clkr,
|
|
[SPARE_I2S_MIC_BIT_DIV_CLK] = &spare_i2s_mic_bit_div_clk.clkr,
|
|
[SPARE_I2S_MIC_BIT_CLK] = &spare_i2s_mic_bit_clk.clkr,
|
|
[CODEC_I2S_SPKR_OSR_SRC] = &codec_i2s_spkr_osr_src.clkr,
|
|
[CODEC_I2S_SPKR_OSR_CLK] = &codec_i2s_spkr_osr_clk.clkr,
|
|
[CODEC_I2S_SPKR_DIV_CLK] = &codec_i2s_spkr_div_clk.clkr,
|
|
[CODEC_I2S_SPKR_BIT_DIV_CLK] = &codec_i2s_spkr_bit_div_clk.clkr,
|
|
[CODEC_I2S_SPKR_BIT_CLK] = &codec_i2s_spkr_bit_clk.clkr,
|
|
[SPARE_I2S_SPKR_OSR_SRC] = &spare_i2s_spkr_osr_src.clkr,
|
|
[SPARE_I2S_SPKR_OSR_CLK] = &spare_i2s_spkr_osr_clk.clkr,
|
|
[SPARE_I2S_SPKR_DIV_CLK] = &spare_i2s_spkr_div_clk.clkr,
|
|
[SPARE_I2S_SPKR_BIT_DIV_CLK] = &spare_i2s_spkr_bit_div_clk.clkr,
|
|
[SPARE_I2S_SPKR_BIT_CLK] = &spare_i2s_spkr_bit_clk.clkr,
|
|
};
|
|
|
|
static const struct regmap_config lcc_mdm9615_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0xfc,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static const struct qcom_cc_desc lcc_mdm9615_desc = {
|
|
.config = &lcc_mdm9615_regmap_config,
|
|
.clks = lcc_mdm9615_clks,
|
|
.num_clks = ARRAY_SIZE(lcc_mdm9615_clks),
|
|
};
|
|
|
|
static const struct of_device_id lcc_mdm9615_match_table[] = {
|
|
{ .compatible = "qcom,lcc-mdm9615" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, lcc_mdm9615_match_table);
|
|
|
|
static int lcc_mdm9615_probe(struct platform_device *pdev)
|
|
{
|
|
u32 val;
|
|
struct regmap *regmap;
|
|
|
|
regmap = qcom_cc_map(pdev, &lcc_mdm9615_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
/* Use the correct frequency plan depending on speed of PLL4 */
|
|
regmap_read(regmap, 0x4, &val);
|
|
if (val == 0x12) {
|
|
slimbus_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
codec_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
spare_i2s_mic_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
codec_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
spare_i2s_spkr_osr_src.freq_tbl = clk_tbl_aif_osr_492;
|
|
pcm_src.freq_tbl = clk_tbl_pcm_492;
|
|
}
|
|
/* Enable PLL4 source on the LPASS Primary PLL Mux */
|
|
regmap_write(regmap, 0xc4, 0x1);
|
|
|
|
return qcom_cc_really_probe(pdev, &lcc_mdm9615_desc, regmap);
|
|
}
|
|
|
|
static struct platform_driver lcc_mdm9615_driver = {
|
|
.probe = lcc_mdm9615_probe,
|
|
.driver = {
|
|
.name = "lcc-mdm9615",
|
|
.of_match_table = lcc_mdm9615_match_table,
|
|
},
|
|
};
|
|
module_platform_driver(lcc_mdm9615_driver);
|
|
|
|
MODULE_DESCRIPTION("QCOM LCC MDM9615 Driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:lcc-mdm9615");
|