266 lines
6.4 KiB
C
266 lines
6.4 KiB
C
/*
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* Broadcom STB SoCs Bus Unit Interface controls
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*
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* Copyright (C) 2015, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/syscore_ops.h>
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#include <linux/soc/brcmstb/brcmstb.h>
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#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
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#define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
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#define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
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#define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
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#define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
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#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
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#define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
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#define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
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static void __iomem *cpubiuctrl_base;
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static bool mcp_wr_pairing_en;
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static const int *cpubiuctrl_regs;
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static inline u32 cbc_readl(int reg)
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{
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int offset = cpubiuctrl_regs[reg];
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if (offset == -1)
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return (u32)-1;
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return readl_relaxed(cpubiuctrl_base + offset);
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}
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static inline void cbc_writel(u32 val, int reg)
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{
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int offset = cpubiuctrl_regs[reg];
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if (offset == -1)
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return;
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writel(val, cpubiuctrl_base + offset);
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}
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enum cpubiuctrl_regs {
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CPU_CREDIT_REG = 0,
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CPU_MCP_FLOW_REG,
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CPU_WRITEBACK_CTRL_REG
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};
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static const int b15_cpubiuctrl_regs[] = {
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[CPU_CREDIT_REG] = 0x184,
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[CPU_MCP_FLOW_REG] = -1,
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[CPU_WRITEBACK_CTRL_REG] = -1,
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};
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/* Odd cases, e.g: 7260 */
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static const int b53_cpubiuctrl_no_wb_regs[] = {
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[CPU_CREDIT_REG] = 0x0b0,
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[CPU_MCP_FLOW_REG] = 0x0b4,
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[CPU_WRITEBACK_CTRL_REG] = -1,
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};
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static const int b53_cpubiuctrl_regs[] = {
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[CPU_CREDIT_REG] = 0x0b0,
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[CPU_MCP_FLOW_REG] = 0x0b4,
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[CPU_WRITEBACK_CTRL_REG] = 0x22c,
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};
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#define NUM_CPU_BIUCTRL_REGS 3
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static int __init mcp_write_pairing_set(void)
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{
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u32 creds = 0;
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if (!cpubiuctrl_base)
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return -1;
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creds = cbc_readl(CPU_CREDIT_REG);
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if (mcp_wr_pairing_en) {
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pr_info("MCP: Enabling write pairing\n");
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cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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CPU_CREDIT_REG);
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} else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
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pr_info("MCP: Disabling write pairing\n");
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cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
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CPU_CREDIT_REG);
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} else {
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pr_info("MCP: Write pairing already disabled\n");
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}
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return 0;
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}
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static const u32 b53_mach_compat[] = {
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0x7268,
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0x7271,
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0x7278,
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};
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static void __init mcp_b53_set(void)
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{
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unsigned int i;
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u32 reg;
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reg = brcmstb_get_family_id();
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for (i = 0; i < ARRAY_SIZE(b53_mach_compat); i++) {
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if (BRCM_ID(reg) == b53_mach_compat[i])
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break;
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}
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if (i == ARRAY_SIZE(b53_mach_compat))
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return;
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/* Set all 3 MCP interfaces to 8 credits */
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reg = cbc_readl(CPU_CREDIT_REG);
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for (i = 0; i < 3; i++) {
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reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
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CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
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reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
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CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
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reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
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reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
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}
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cbc_writel(reg, CPU_CREDIT_REG);
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/* Max out the number of in-flight Jwords reads on the MCP interface */
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reg = cbc_readl(CPU_MCP_FLOW_REG);
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for (i = 0; i < 3; i++)
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reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
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CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
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cbc_writel(reg, CPU_MCP_FLOW_REG);
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/* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
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* threshold
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*/
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reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
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reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
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reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
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reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
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CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
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reg |= 8;
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reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
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cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
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}
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static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
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{
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struct device_node *cpu_dn;
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int ret = 0;
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cpubiuctrl_base = of_iomap(np, 0);
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if (!cpubiuctrl_base) {
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pr_err("failed to remap BIU control base\n");
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ret = -ENOMEM;
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goto out;
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}
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mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
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cpu_dn = of_get_cpu_node(0, NULL);
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if (!cpu_dn) {
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pr_err("failed to obtain CPU device node\n");
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ret = -ENODEV;
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goto out;
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}
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if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
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cpubiuctrl_regs = b15_cpubiuctrl_regs;
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else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
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cpubiuctrl_regs = b53_cpubiuctrl_regs;
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else {
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pr_err("unsupported CPU\n");
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ret = -EINVAL;
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}
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of_node_put(cpu_dn);
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if (BRCM_ID(brcmstb_get_family_id()) == 0x7260)
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cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
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out:
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of_node_put(np);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
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static int brcmstb_cpu_credit_reg_suspend(void)
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{
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unsigned int i;
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if (!cpubiuctrl_base)
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return 0;
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for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
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cpubiuctrl_reg_save[i] = cbc_readl(i);
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return 0;
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}
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static void brcmstb_cpu_credit_reg_resume(void)
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{
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unsigned int i;
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if (!cpubiuctrl_base)
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return;
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for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
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cbc_writel(cpubiuctrl_reg_save[i], i);
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}
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static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
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.suspend = brcmstb_cpu_credit_reg_suspend,
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.resume = brcmstb_cpu_credit_reg_resume,
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};
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#endif
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static int __init brcmstb_biuctrl_init(void)
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{
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struct device_node *np;
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int ret;
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/* We might be running on a multi-platform kernel, don't make this a
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* fatal error, just bail out early
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*/
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np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
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if (!np)
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return 0;
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ret = setup_hifcpubiuctrl_regs(np);
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if (ret)
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return ret;
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ret = mcp_write_pairing_set();
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if (ret) {
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pr_err("MCP: Unable to disable write pairing!\n");
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return ret;
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}
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mcp_b53_set();
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#ifdef CONFIG_PM_SLEEP
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register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
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#endif
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return 0;
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}
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early_initcall(brcmstb_biuctrl_init);
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