199 lines
5.2 KiB
C
199 lines
5.2 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* Authors: Christian König <christian.koenig@amd.com>
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*/
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "radeon_asic.h"
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#include "cikd.h"
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#define VCE_V2_0_FW_SIZE (256 * 1024)
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#define VCE_V2_0_STACK_SIZE (64 * 1024)
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#define VCE_V2_0_DATA_SIZE (23552 * RADEON_MAX_VCE_HANDLES)
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static void vce_v2_0_set_sw_cg(struct radeon_device *rdev, bool gated)
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{
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u32 tmp;
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if (gated) {
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tmp = RREG32(VCE_CLOCK_GATING_B);
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tmp |= 0xe70000;
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WREG32(VCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp |= 0xff000000;
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
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} else {
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tmp = RREG32(VCE_CLOCK_GATING_B);
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tmp |= 0xe7;
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tmp &= ~0xe70000;
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WREG32(VCE_CLOCK_GATING_B, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp |= 0x1fe000;
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tmp &= ~0xff000000;
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp |= 0x3fc;
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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}
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}
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static void vce_v2_0_set_dyn_cg(struct radeon_device *rdev, bool gated)
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{
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u32 orig, tmp;
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tmp = RREG32(VCE_CLOCK_GATING_B);
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tmp &= ~0x00060006;
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if (gated) {
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tmp |= 0xe10000;
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} else {
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tmp |= 0xe1;
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tmp &= ~0xe10000;
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}
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WREG32(VCE_CLOCK_GATING_B, tmp);
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orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp &= ~0x1fe000;
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tmp &= ~0xff000000;
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if (tmp != orig)
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
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tmp &= ~0x3fc;
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if (tmp != orig)
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WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
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if (gated)
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WREG32(VCE_CGTT_CLK_OVERRIDE, 0);
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}
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static void vce_v2_0_disable_cg(struct radeon_device *rdev)
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{
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WREG32(VCE_CGTT_CLK_OVERRIDE, 7);
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}
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/*
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* Local variable sw_cg is used for debugging purposes, in case we
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* ran into problems with dynamic clock gating. Don't remove it.
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*/
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void vce_v2_0_enable_mgcg(struct radeon_device *rdev, bool enable)
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{
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bool sw_cg = false;
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if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
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if (sw_cg)
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vce_v2_0_set_sw_cg(rdev, true);
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else
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vce_v2_0_set_dyn_cg(rdev, true);
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} else {
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vce_v2_0_disable_cg(rdev);
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if (sw_cg)
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vce_v2_0_set_sw_cg(rdev, false);
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else
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vce_v2_0_set_dyn_cg(rdev, false);
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}
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}
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static void vce_v2_0_init_cg(struct radeon_device *rdev)
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{
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u32 tmp;
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tmp = RREG32(VCE_CLOCK_GATING_A);
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tmp &= ~(CGC_CLK_GATE_DLY_TIMER_MASK | CGC_CLK_GATER_OFF_DLY_TIMER_MASK);
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tmp |= (CGC_CLK_GATE_DLY_TIMER(0) | CGC_CLK_GATER_OFF_DLY_TIMER(4));
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tmp |= CGC_UENC_WAIT_AWAKE;
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WREG32(VCE_CLOCK_GATING_A, tmp);
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tmp = RREG32(VCE_UENC_CLOCK_GATING);
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tmp &= ~(CLOCK_ON_DELAY_MASK | CLOCK_OFF_DELAY_MASK);
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tmp |= (CLOCK_ON_DELAY(0) | CLOCK_OFF_DELAY(4));
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WREG32(VCE_UENC_CLOCK_GATING, tmp);
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tmp = RREG32(VCE_CLOCK_GATING_B);
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tmp |= 0x10;
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tmp &= ~0x100000;
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WREG32(VCE_CLOCK_GATING_B, tmp);
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}
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unsigned vce_v2_0_bo_size(struct radeon_device *rdev)
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{
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WARN_ON(rdev->vce_fw->size > VCE_V2_0_FW_SIZE);
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return VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE;
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}
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int vce_v2_0_resume(struct radeon_device *rdev)
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{
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uint64_t addr = rdev->vce.gpu_addr;
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uint32_t size;
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WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
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WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
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WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
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WREG32(VCE_CLOCK_GATING_B, 0xf7);
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WREG32(VCE_LMI_CTRL, 0x00398000);
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WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
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WREG32(VCE_LMI_SWAP_CNTL, 0);
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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addr &= 0xff;
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size = VCE_V2_0_FW_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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addr += size;
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size = VCE_V2_0_STACK_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE1, size);
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addr += size;
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size = VCE_V2_0_DATA_SIZE;
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WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE2, size);
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WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
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WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
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~VCE_SYS_INT_TRAP_INTERRUPT_EN);
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vce_v2_0_init_cg(rdev);
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return 0;
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}
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