237 lines
7.6 KiB
C
237 lines
7.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#ifndef _ASM_IA64_SN_BTE_H
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#define _ASM_IA64_SN_BTE_H
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#include <linux/timer.h>
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#include <linux/spinlock.h>
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#include <linux/cache.h>
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#include <asm/sn/pda.h>
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#include <asm/sn/types.h>
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#include <asm/sn/shub_mmr.h>
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struct nodepda_s;
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#define IBCT_NOTIFY (0x1UL << 4)
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#define IBCT_ZFIL_MODE (0x1UL << 0)
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/* #define BTE_DEBUG */
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/* #define BTE_DEBUG_VERBOSE */
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#ifdef BTE_DEBUG
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# define BTE_PRINTK(x) printk x /* Terse */
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# ifdef BTE_DEBUG_VERBOSE
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# define BTE_PRINTKV(x) printk x /* Verbose */
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# else
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# define BTE_PRINTKV(x)
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# endif /* BTE_DEBUG_VERBOSE */
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#else
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# define BTE_PRINTK(x)
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# define BTE_PRINTKV(x)
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#endif /* BTE_DEBUG */
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/* BTE status register only supports 16 bits for length field */
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#define BTE_LEN_BITS (16)
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#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
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#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
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/* Define hardware */
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#define BTES_PER_NODE (is_shub2() ? 4 : 2)
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#define MAX_BTES_PER_NODE 4
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#define BTE2OFF_CTRL 0
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#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
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#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
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#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
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#define BTE_BASE_ADDR(interface) \
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(is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
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(interface == 1) ? SH2_BT_ENG_CSR_1 : \
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(interface == 2) ? SH2_BT_ENG_CSR_2 : \
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SH2_BT_ENG_CSR_3 \
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: (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
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#define BTE_SOURCE_ADDR(base) \
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(is_shub2() ? base + (BTE2OFF_SRC/8) \
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: base + (BTEOFF_SRC/8))
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#define BTE_DEST_ADDR(base) \
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(is_shub2() ? base + (BTE2OFF_DEST/8) \
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: base + (BTEOFF_DEST/8))
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#define BTE_CTRL_ADDR(base) \
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(is_shub2() ? base + (BTE2OFF_CTRL/8) \
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: base + (BTEOFF_CTRL/8))
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#define BTE_NOTIF_ADDR(base) \
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(is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
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: base + (BTEOFF_NOTIFY/8))
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/* Define hardware modes */
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#define BTE_NOTIFY IBCT_NOTIFY
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#define BTE_NORMAL BTE_NOTIFY
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#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
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/* Use a reserved bit to let the caller specify a wait for any BTE */
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#define BTE_WACQUIRE 0x4000
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/* Use the BTE on the node with the destination memory */
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#define BTE_USE_DEST (BTE_WACQUIRE << 1)
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/* Use any available BTE interface on any node for the transfer */
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#define BTE_USE_ANY (BTE_USE_DEST << 1)
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/* macro to force the IBCT0 value valid */
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#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
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#define BTE_ACTIVE (IBLS_BUSY | IBLS_ERROR)
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#define BTE_WORD_AVAILABLE (IBLS_BUSY << 1)
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#define BTE_WORD_BUSY (~BTE_WORD_AVAILABLE)
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/*
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* Some macros to simplify reading.
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* Start with macros to locate the BTE control registers.
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*/
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#define BTE_LNSTAT_LOAD(_bte) \
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HUB_L(_bte->bte_base_addr)
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#define BTE_LNSTAT_STORE(_bte, _x) \
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HUB_S(_bte->bte_base_addr, (_x))
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#define BTE_SRC_STORE(_bte, _x) \
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({ \
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u64 __addr = ((_x) & ~AS_MASK); \
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if (is_shub2()) \
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__addr = SH2_TIO_PHYS_TO_DMA(__addr); \
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HUB_S(_bte->bte_source_addr, __addr); \
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})
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#define BTE_DEST_STORE(_bte, _x) \
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({ \
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u64 __addr = ((_x) & ~AS_MASK); \
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if (is_shub2()) \
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__addr = SH2_TIO_PHYS_TO_DMA(__addr); \
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HUB_S(_bte->bte_destination_addr, __addr); \
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})
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#define BTE_CTRL_STORE(_bte, _x) \
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HUB_S(_bte->bte_control_addr, (_x))
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#define BTE_NOTIF_STORE(_bte, _x) \
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({ \
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u64 __addr = ia64_tpa((_x) & ~AS_MASK); \
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if (is_shub2()) \
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__addr = SH2_TIO_PHYS_TO_DMA(__addr); \
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HUB_S(_bte->bte_notify_addr, __addr); \
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})
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#define BTE_START_TRANSFER(_bte, _len, _mode) \
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is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
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: BTE_LNSTAT_STORE(_bte, _len); \
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BTE_CTRL_STORE(_bte, _mode)
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/* Possible results from bte_copy and bte_unaligned_copy */
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/* The following error codes map into the BTE hardware codes
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* IIO_ICRB_ECODE_* (in shubio.h). The hardware uses
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* an error code of 0 (IIO_ICRB_ECODE_DERR), but we want zero
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* to mean BTE_SUCCESS, so add one (BTEFAIL_OFFSET) to the error
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* codes to give the following error codes.
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*/
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#define BTEFAIL_OFFSET 1
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typedef enum {
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BTE_SUCCESS, /* 0 is success */
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BTEFAIL_DIR, /* Directory error due to IIO access*/
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BTEFAIL_POISON, /* poison error on IO access (write to poison page) */
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BTEFAIL_WERR, /* Write error (ie WINV to a Read only line) */
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BTEFAIL_ACCESS, /* access error (protection violation) */
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BTEFAIL_PWERR, /* Partial Write Error */
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BTEFAIL_PRERR, /* Partial Read Error */
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BTEFAIL_TOUT, /* CRB Time out */
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BTEFAIL_XTERR, /* Incoming xtalk pkt had error bit */
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BTEFAIL_NOTAVAIL, /* BTE not available */
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} bte_result_t;
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#define BTEFAIL_SH2_RESP_SHORT 0x1 /* bit 000001 */
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#define BTEFAIL_SH2_RESP_LONG 0x2 /* bit 000010 */
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#define BTEFAIL_SH2_RESP_DSP 0x4 /* bit 000100 */
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#define BTEFAIL_SH2_RESP_ACCESS 0x8 /* bit 001000 */
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#define BTEFAIL_SH2_CRB_TO 0x10 /* bit 010000 */
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#define BTEFAIL_SH2_NACK_LIMIT 0x20 /* bit 100000 */
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#define BTEFAIL_SH2_ALL 0x3F /* bit 111111 */
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#define BTE_ERR_BITS 0x3FUL
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#define BTE_ERR_SHIFT 36
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#define BTE_ERR_MASK (BTE_ERR_BITS << BTE_ERR_SHIFT)
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#define BTE_ERROR_RETRY(value) \
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(is_shub2() ? (value != BTEFAIL_SH2_CRB_TO) \
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: (value != BTEFAIL_TOUT))
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/*
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* On shub1 BTE_ERR_MASK will always be false, so no need for is_shub2()
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*/
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#define BTE_SHUB2_ERROR(_status) \
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((_status & BTE_ERR_MASK) \
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? (((_status >> BTE_ERR_SHIFT) & BTE_ERR_BITS) | IBLS_ERROR) \
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: _status)
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#define BTE_GET_ERROR_STATUS(_status) \
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(BTE_SHUB2_ERROR(_status) & ~IBLS_ERROR)
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#define BTE_VALID_SH2_ERROR(value) \
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((value >= BTEFAIL_SH2_RESP_SHORT) && (value <= BTEFAIL_SH2_ALL))
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/*
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* Structure defining a bte. An instance of this
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* structure is created in the nodepda for each
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* bte on that node (as defined by BTES_PER_NODE)
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* This structure contains everything necessary
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* to work with a BTE.
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*/
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struct bteinfo_s {
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volatile u64 notify ____cacheline_aligned;
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u64 *bte_base_addr ____cacheline_aligned;
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u64 *bte_source_addr;
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u64 *bte_destination_addr;
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u64 *bte_control_addr;
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u64 *bte_notify_addr;
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spinlock_t spinlock;
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cnodeid_t bte_cnode; /* cnode */
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int bte_error_count; /* Number of errors encountered */
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int bte_num; /* 0 --> BTE0, 1 --> BTE1 */
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int cleanup_active; /* Interface is locked for cleanup */
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volatile bte_result_t bh_error; /* error while processing */
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volatile u64 *most_rcnt_na;
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struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
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};
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/*
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* Function prototypes (functions defined in bte.c, used elsewhere)
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*/
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extern bte_result_t bte_copy(u64, u64, u64, u64, void *);
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extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64);
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extern void bte_error_handler(struct nodepda_s *);
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#define bte_zero(dest, len, mode, notification) \
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bte_copy(0, dest, len, ((mode) | BTE_ZERO_FILL), notification)
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/*
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* The following is the preferred way of calling bte_unaligned_copy
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* If the copy is fully cache line aligned, then bte_copy is
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* used instead. Since bte_copy is inlined, this saves a call
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* stack. NOTE: bte_copy is called synchronously and does block
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* until the transfer is complete. In order to get the asynch
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* version of bte_copy, you must perform this check yourself.
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*/
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#define BTE_UNALIGNED_COPY(src, dest, len, mode) \
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(((len & (L1_CACHE_BYTES - 1)) || \
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(src & (L1_CACHE_BYTES - 1)) || \
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(dest & (L1_CACHE_BYTES - 1))) ? \
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bte_unaligned_copy(src, dest, len, mode) : \
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bte_copy(src, dest, len, mode, NULL))
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#endif /* _ASM_IA64_SN_BTE_H */
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