72 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			72 lines
		
	
	
		
			1.8 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| config USB_DWC3
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| 	bool "DesignWare USB3 DRD Core Support"
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| 	depends on USB_HOST || USB_GADGET
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| 	help
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| 	  Say Y here if your system has a Dual Role SuperSpeed
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| 	  USB controller based on the DesignWare USB3 IP Core.
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| 
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| if USB_DWC3
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| 
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| choice
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| 	bool "DWC3 Mode Selection"
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| 
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| config USB_DWC3_HOST
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| 	bool "Host only mode"
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| 	depends on USB
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| 	help
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| 	  Select this when you want to use DWC3 in host mode only,
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| 	  thereby the gadget feature will be regressed.
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| 
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| config USB_DWC3_GADGET
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| 	bool "Gadget only mode"
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| 	depends on USB_GADGET
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| 	select USB_GADGET_DUALSPEED
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| 	help
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| 	  Select this when you want to use DWC3 in gadget mode only,
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| 	  thereby the host feature will be regressed.
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| 
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| endchoice
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| 
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| comment "Platform Glue Driver Support"
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| 
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| config USB_DWC3_OMAP
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| 	bool "Texas Instruments OMAP5 and similar Platforms"
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| 	help
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| 	  Some platforms from Texas Instruments like OMAP5, DRA7xxx and
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| 	  AM437x use this IP for USB2/3 functionality.
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| 
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| 	  Say 'Y' here if you have one such device
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| 
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| config USB_DWC3_GENERIC
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| 	bool "Generic implementation of a DWC3 wrapper (aka dwc3 glue)"
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| 	depends on DM_USB && USB_DWC3 && MISC
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| 	help
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| 	  Select this for Xilinx ZynqMP and similar Platforms.
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| 	  This wrapper supports Host and Peripheral operation modes.
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| 
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| config USB_DWC3_UNIPHIER
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| 	bool "DesignWare USB3 Host Support on UniPhier Platforms"
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| 	depends on ARCH_UNIPHIER && USB_XHCI_DWC3
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| 	help
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| 	  Support of USB2/3 functionality in Socionext UniPhier platforms.
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| 	  Say 'Y' here if you have one such device.
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| 
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| menu "PHY Subsystem"
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| 
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| config USB_DWC3_PHY_OMAP
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| 	bool "TI OMAP SoC series USB DRD PHY driver"
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| 	help
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| 	  Enable single driver for both USB2 PHY programming and USB3 PHY
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| 	  programming for TI SoCs.
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| 
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| config USB_DWC3_PHY_SAMSUNG
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| 	bool "Exynos5 SoC series USB DRD PHY driver"
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| 	help
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| 	  Enable USB DRD PHY support for Exynos 5 SoC series.
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| 	  This driver provides PHY interface for USB 3.0 DRD controller
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| 	  present on Exynos5 SoC series.
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| 
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| endmenu
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| 
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| endif
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