384 lines
12 KiB
C
384 lines
12 KiB
C
/*
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* PS3 Platfom gelic network driver.
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*
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* Copyright (C) 2007 Sony Computer Entertainment Inc.
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* Copyright 2006, 2007 Sony Corporation.
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*
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* This file is based on: spider_net.h
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*
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* (C) Copyright IBM Corp. 2005
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*
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* Authors : Utz Bacher <utz.bacher@de.ibm.com>
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* Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef _GELIC_NET_H
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#define _GELIC_NET_H
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/* descriptors */
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#define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
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#define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
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#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
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#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
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#define GELIC_NET_RXBUF_ALIGN 128
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#define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */
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#define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
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#define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
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#define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
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/* virtual interrupt status register bits */
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/* INT1 */
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#define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
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#define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
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#define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
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#define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
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#define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
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#define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
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#define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
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#define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
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#define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
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#define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
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#define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
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#define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
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#define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
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#define GELIC_CARD_WLAN_EVENT_RECEIVED 0x0000000040000000L
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#define GELIC_CARD_WLAN_COMMAND_COMPLETED 0x0000000080000000L
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/* INT 0 */
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#define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
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#define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
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#define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
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#define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
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#define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
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#define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
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#define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
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/* initial interrupt mask */
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#define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
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#define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
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GELIC_CARD_NUMBER_OF_RX_FRAME)
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/* RX descriptor data_status bits */
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enum gelic_descr_rx_status {
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GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */
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GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */
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GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */
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GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */
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GELIC_DESCR_RXWTPKT = 0x00C00000, /*
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* wakeup trigger packet
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* 01: Magic Packet (TM)
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* 10: ARP packet
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* 11: Multicast MAC addr
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*/
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GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */
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/* bit 20..16 reserved */
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GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */
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/* bit 7..0 reserved */
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};
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#define GELIC_DESCR_DATA_STATUS_CHK_MASK \
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(GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
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/* TX descriptor data_status bits */
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enum gelic_descr_tx_status {
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GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this
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* descriptor was end of
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* a tx frame
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*/
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};
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/* RX descriptor data error bits */
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enum gelic_descr_rx_error {
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/* bit 31 reserved */
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GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */
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GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */
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GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */
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GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */
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GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */
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GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */
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GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */
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/* bit 18 reserved */
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GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */
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GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length
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* error */
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GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extension error */
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GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */
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/* bit 13..0 reserved */
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};
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#define GELIC_DESCR_DATA_ERROR_CHK_MASK \
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(GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
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/* DMA command and status (RX and TX)*/
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enum gelic_descr_dma_status {
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GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */
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GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */
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GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */
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GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */
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GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */
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GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */
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GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */
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GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */
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};
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#define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
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/* tx descriptor command and status */
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enum gelic_descr_tx_dma_status {
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/* [19] */
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GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */
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/* [18] */
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GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of
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* the packet
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*/
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/* [17..16] */
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GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */
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GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */
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GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */
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/* [1] */
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GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
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* due to chain end
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*/
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};
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#define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_NO_CHKSUM)
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#define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_TCP_CHKSUM)
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#define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
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(GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
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GELIC_DESCR_TX_DMA_UDP_CHKSUM)
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enum gelic_descr_rx_dma_status {
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/* [ 1 ] */
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GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated
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* due to chain end
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*/
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};
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/* for lv1_net_control */
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enum gelic_lv1_net_control_code {
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GELIC_LV1_GET_MAC_ADDRESS = 1,
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GELIC_LV1_GET_ETH_PORT_STATUS = 2,
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GELIC_LV1_SET_NEGOTIATION_MODE = 3,
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GELIC_LV1_GET_VLAN_ID = 4,
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GELIC_LV1_SET_WOL = 5,
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GELIC_LV1_GET_CHANNEL = 6,
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GELIC_LV1_POST_WLAN_CMD = 9,
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GELIC_LV1_GET_WLAN_CMD_RESULT = 10,
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GELIC_LV1_GET_WLAN_EVENT = 11,
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};
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/* for GELIC_LV1_SET_WOL */
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enum gelic_lv1_wol_command {
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GELIC_LV1_WOL_MAGIC_PACKET = 1,
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GELIC_LV1_WOL_ADD_MATCH_ADDR = 6,
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GELIC_LV1_WOL_DELETE_MATCH_ADDR = 7,
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};
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/* for GELIC_LV1_WOL_MAGIC_PACKET */
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enum gelic_lv1_wol_mp_arg {
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GELIC_LV1_WOL_MP_DISABLE = 0,
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GELIC_LV1_WOL_MP_ENABLE = 1,
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};
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/* for GELIC_LV1_WOL_{ADD,DELETE}_MATCH_ADDR */
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enum gelic_lv1_wol_match_arg {
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GELIC_LV1_WOL_MATCH_INDIVIDUAL = 0,
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GELIC_LV1_WOL_MATCH_ALL = 1,
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};
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/* status returened from GET_ETH_PORT_STATUS */
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enum gelic_lv1_ether_port_status {
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GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L,
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GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L,
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GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L,
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GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L,
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GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L,
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GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L,
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GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L,
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};
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enum gelic_lv1_vlan_index {
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/* for outgoing packets */
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GELIC_LV1_VLAN_TX_ETHERNET_0 = 0x0000000000000002L,
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GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L,
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/* for incoming packets */
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GELIC_LV1_VLAN_RX_ETHERNET_0 = 0x0000000000000012L,
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GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L,
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};
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enum gelic_lv1_phy {
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GELIC_LV1_PHY_ETHERNET_0 = 0x0000000000000002L,
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};
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/* size of hardware part of gelic descriptor */
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#define GELIC_DESCR_SIZE (32)
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enum gelic_port_type {
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GELIC_PORT_ETHERNET_0 = 0,
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GELIC_PORT_WIRELESS = 1,
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GELIC_PORT_MAX
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};
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struct gelic_descr {
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/* as defined by the hardware */
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__be32 buf_addr;
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__be32 buf_size;
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__be32 next_descr_addr;
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__be32 dmac_cmd_status;
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__be32 result_size;
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__be32 valid_size; /* all zeroes for tx */
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__be32 data_status;
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__be32 data_error; /* all zeroes for tx */
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/* used in the driver */
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struct sk_buff *skb;
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dma_addr_t bus_addr;
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struct gelic_descr *next;
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struct gelic_descr *prev;
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} __attribute__((aligned(32)));
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struct gelic_descr_chain {
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/* we walk from tail to head */
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struct gelic_descr *head;
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struct gelic_descr *tail;
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};
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struct gelic_vlan_id {
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u16 tx;
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u16 rx;
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};
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struct gelic_card {
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struct napi_struct napi;
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struct net_device *netdev[GELIC_PORT_MAX];
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/*
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* hypervisor requires irq_status should be
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* 8 bytes aligned, but u64 member is
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* always disposed in that manner
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*/
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u64 irq_status;
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u64 irq_mask;
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struct ps3_system_bus_device *dev;
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struct gelic_vlan_id vlan[GELIC_PORT_MAX];
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int vlan_required;
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struct gelic_descr_chain tx_chain;
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struct gelic_descr_chain rx_chain;
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/*
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* tx_lock guards tx descriptor list and
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* tx_dma_progress.
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*/
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spinlock_t tx_lock;
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int tx_dma_progress;
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struct work_struct tx_timeout_task;
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atomic_t tx_timeout_task_counter;
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wait_queue_head_t waitq;
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/* only first user should up the card */
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struct mutex updown_lock;
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atomic_t users;
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u64 ether_port_status;
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int link_mode;
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/* original address returned by kzalloc */
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void *unalign;
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/*
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* each netdevice has copy of irq
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*/
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unsigned int irq;
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struct gelic_descr *tx_top, *rx_top;
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struct gelic_descr descr[0]; /* must be the last */
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};
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struct gelic_port {
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struct gelic_card *card;
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struct net_device *netdev;
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enum gelic_port_type type;
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long priv[0]; /* long for alignment */
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};
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static inline struct gelic_card *port_to_card(struct gelic_port *p)
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{
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return p->card;
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}
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static inline struct net_device *port_to_netdev(struct gelic_port *p)
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{
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return p->netdev;
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}
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static inline struct gelic_card *netdev_card(struct net_device *d)
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{
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return ((struct gelic_port *)netdev_priv(d))->card;
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}
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static inline struct gelic_port *netdev_port(struct net_device *d)
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{
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return (struct gelic_port *)netdev_priv(d);
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}
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static inline struct device *ctodev(struct gelic_card *card)
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{
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return &card->dev->core;
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}
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static inline u64 bus_id(struct gelic_card *card)
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{
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return card->dev->bus_id;
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}
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static inline u64 dev_id(struct gelic_card *card)
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{
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return card->dev->dev_id;
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}
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static inline void *port_priv(struct gelic_port *port)
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{
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return port->priv;
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}
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#ifdef CONFIG_PPC_EARLY_DEBUG_PS3GELIC
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void udbg_shutdown_ps3gelic(void);
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#else
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static inline void udbg_shutdown_ps3gelic(void) {}
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#endif
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int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
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/* shared netdev ops */
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void gelic_card_up(struct gelic_card *card);
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void gelic_card_down(struct gelic_card *card);
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int gelic_net_open(struct net_device *netdev);
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int gelic_net_stop(struct net_device *netdev);
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netdev_tx_t gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
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void gelic_net_set_multi(struct net_device *netdev);
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void gelic_net_tx_timeout(struct net_device *netdev);
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int gelic_net_setup_netdev(struct net_device *netdev, struct gelic_card *card);
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/* shared ethtool ops */
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void gelic_net_get_drvinfo(struct net_device *netdev,
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struct ethtool_drvinfo *info);
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void gelic_net_poll_controller(struct net_device *netdev);
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#endif /* _GELIC_NET_H */
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