196 lines
5.8 KiB
C
Executable File
196 lines
5.8 KiB
C
Executable File
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#ifndef _ASM_ARMV8_GIC_H_
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#define _ASM_ARMV8_GIC_H_
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//#include "FLibARM.h"
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#define UART_INTID 43
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#define GIC_UART_INTID (UART_INTID + 32)
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#if 0
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/*
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* Distributor layout
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*/
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IIDR 0x0008
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#define GICD_IGROUP 0x0080
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#define GICD_ISENABLE 0x0100
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#define GICD_ICENABLE 0x0180
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#define GICD_ISPEND 0x0200
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#define GICD_ICPEND 0x0280
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#define GICD_ISACTIVE 0x0300
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#define GICD_ICACTIVE 0x0380
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#define GICD_IPRIORITY 0x0400
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#define GICD_ITARGETS 0x0800
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#define GICD_ICFG 0x0c00
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#define GICD_PPISR 0x0d00
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#define GICD_SPISR 0x0d04
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#define GICD_SGIR 0x0f00
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#define GICD_CPENDSGI 0x0f10
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#define GICD_SPENDSGI 0x0f20
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#define GICD_PIDR4 0x0fd0
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#define GICD_PIDR5 0x0fd4
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#define GICD_PIDR6 0x0fd8
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#define GICD_PIDR7 0x0fdc
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#define GICD_PIDR0 0x0fe0
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#define GICD_PIDR1 0x0fe4
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#define GICD_PIDR2 0x0fe8
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#define GICD_PIDR3 0x0fec
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#define GICD_CIDR0 0x0ff0
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#define GICD_CIDR1 0x0ff4
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#define GICD_CIDR2 0x0ff8
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#define GICD_CIDR3 0x0ffc
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/*
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* CPU Interface layout
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*/
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#define GICC_CTLR 0x0000
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#define GICC_PMR 0x0004
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#define GICC_BPR 0x0008
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#define GICC_IAR 0x000c
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#define GICC_EOIR 0x0010
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#define GICC_RPR 0x0014
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#define GICC_HPPIR 0x0018
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#define GICC_ABPR 0x001c
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#define GICC_AIAR 0x0020
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#define GICC_AEOIR 0x0024
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#define GICC_AHPPIR 0x0028
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#define GICC_APR0 0x00d0
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#define GICC_NSAPR0 0x00e0
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#define GICC_IIDR 0x00fc
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#define GICC_DIR 0x1000
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#endif
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#define MAX_SPIS 480
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#define MAX_PPIS 14
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#define MAX_SGIS 16
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#define MIN_SGI_ID 0
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#define MIN_PPI_ID 16
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#define MIN_SPI_ID 32
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#define GRP0 0
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#define GRP1 1
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#define _GICD_ 0x1000
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#define _GICC_ 0x2000
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#define _GICH_ 0x4000
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#define _GICV_ 0x6000
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#define GIC_PRI_MASK 0xff
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#define GIC_HIGHEST_SEC_PRIORITY 0
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#define GIC_LOWEST_SEC_PRIORITY 127
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#define GIC_HIGHEST_NS_PRIORITY 128
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#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */
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#define GIC_SPURIOUS_INTERRUPT 1023
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#define GIC_TARGET_CPU_MASK 0xff
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/* Distributor interface definitions */
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#define GICD_CTLR _GICD_ + 0x0
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#define GICD_TYPER _GICD_ + 0x4
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#define GICD_IGROUPR _GICD_ + 0x80
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#define GICD_ISENABLER _GICD_ + 0x100
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#define GICD_ICENABLER _GICD_ + 0x180
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#define GICD_ISPENDR _GICD_ + 0x200
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#define GICD_ICPENDR _GICD_ + 0x280
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#define GICD_ISACTIVER _GICD_ + 0x300
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#define GICD_ICACTIVER _GICD_ + 0x380
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#define GICD_IPRIORITYR _GICD_ + 0x400
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#define GICD_ITARGETSR _GICD_ + 0x800
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#define GICD_ICFGR _GICD_ + 0xC00
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#define GICD_SGIR _GICD_ + 0xF00
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#define GICD_CPENDSGIR _GICD_ + 0xF10
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#define GICD_SPENDSGIR _GICD_ + 0xF20
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#define IGROUPR_SHIFT 5
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#define ISENABLER_SHIFT 5
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#define ICENABLER_SHIFT ISENABLER_SHIFT
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#define ISPENDR_SHIFT 5
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#define ICPENDR_SHIFT ISPENDR_SHIFT
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#define ISACTIVER_SHIFT 5
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#define ICACTIVER_SHIFT ISACTIVER_SHIFT
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#define IPRIORITYR_SHIFT 2
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#define ITARGETSR_SHIFT 2
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#define ICFGR_SHIFT 4
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#define CPENDSGIR_SHIFT 2
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#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
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/* GICD_TYPER bit definitions */
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#define IT_LINES_NO_MASK 0x1f
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/* GICD_ICFGR bit definitions */
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#define LEVEL_SENSITIVE 0x0
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#define TRIGGER_SENSITIVE 0x1
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/* Physical CPU Interface registers */
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#define GICC_CTLR _GICC_ + 0x0
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#define GICC_PMR _GICC_ + 0x4
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#define GICC_BPR _GICC_ + 0x8
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#define GICC_IAR _GICC_ + 0xC
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#define GICC_EOIR _GICC_ + 0x10
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#define GICC_RPR _GICC_ + 0x14
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#define GICC_HPPIR _GICC_ + 0x18
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#define GICC_AHPPIR _GICC_ + 0x28
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#define GICC_IIDR _GICC_ + 0xFC
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#define GICC_DIR _GICC_ + 0x1000
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#define GICC_PRIODROP _GICC_ + GICC_EOIR
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/* GICC_CTLR bit definitions */
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#define EOI_MODE_NS (1 << 10)
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#define EOI_MODE_S (1 << 9)
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#define IRQ_BYP_DIS_GRP1 (1 << 8)
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#define FIQ_BYP_DIS_GRP1 (1 << 7)
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#define IRQ_BYP_DIS_GRP0 (1 << 6)
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#define FIQ_BYP_DIS_GRP0 (1 << 5)
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#define CBPR (1 << 4)
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#define FIQ_EN (1 << 3)
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#define ACK_CTL (1 << 2)
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#define ENABLE_GRP1 (1 << 1)
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#define ENABLE_GRP0 (1 << 0)
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/* GICC_IIDR bit masks and shifts */
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#define GICC_IIDR_PID_SHIFT 20
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#define GICC_IIDR_ARCH_SHIFT 16
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#define GICC_IIDR_REV_SHIFT 12
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#define GICC_IIDR_IMP_SHIFT 0
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#define GICC_IIDR_PID_MASK 0xfff
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#define GICC_IIDR_ARCH_MASK 0xf
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#define GICC_IIDR_REV_MASK 0xf
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#define GICC_IIDR_IMP_MASK 0xfff
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/* HYP view virtual CPU Interface registers */
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#define GICH_CTL 0x0
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#define GICH_VTR 0x4
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#define GICH_ELRSR0 0x30
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#define GICH_ELRSR1 0x34
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#define GICH_APR0 0xF0
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#define GICH_LR_BASE 0x100
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/* Virtual CPU Interface registers */
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#define GICV_CTL 0x0
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#define GICV_PRIMASK 0x4
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#define GICV_BP 0x8
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#define GICV_INTACK 0xC
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#define GICV_EOI 0x10
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#define GICV_RUNNINGPRI 0x14
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#define GICV_HIGHESTPEND 0x18
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#define GICV_DEACTIVATE 0x1000
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extern void nvt_enable_irq(int number);
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extern void nvt_disable_irq(int number);
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extern void arm_gic_cpuif_setup(void);
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extern void arm_gic_distif_setup(void);
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extern void gicd_write_igroupr(UINT32 id, UINT32 val);
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extern void gicd_write_ipriorityr(UINT32 id, UINT32 val);
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extern UINT32 gicc_get_IAR(void);
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extern void gicc_set_EOIR(UINT32 val);
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#endif /* _ASM_ARMV8_GIC_H_ */
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