209 lines
5.3 KiB
C
209 lines
5.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Atmel Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9x5_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <debug_uart.h>
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#include <asm/mach-types.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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void at91_prepare_cpu_var(void);
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#ifdef CONFIG_CMD_NAND
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static void at91sam9x5ek_nand_hw_init(void)
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{
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
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/* NAND flash on D16 */
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csa |= AT91_MATRIX_NFD0_ON_D16;
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/* Configure IO drive */
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csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
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AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_MODE_TDF_CYCLE(1),
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&smc->cs[3].mode);
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at91_periph_clk_enable(ATMEL_ID_PIOCD);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
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at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_DM_VIDEO
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at91_video_show_board_info();
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#endif
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at91_prepare_cpu_var();
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return 0;
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}
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#endif
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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at91_seriald_hw_init();
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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#ifdef CONFIG_DEBUG_UART
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debug_uart_init();
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#endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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/* arch number of AT91SAM9X5EK-Board */
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_CMD_NAND
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at91sam9x5ek_nand_hw_init();
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#endif
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#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
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at91_uhp_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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#include <nand.h>
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void at91_spl_board_init(void)
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{
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#ifdef CONFIG_SD_BOOT
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at91_mci_hw_init();
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#elif CONFIG_NAND_BOOT
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at91sam9x5ek_nand_hw_init();
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#endif
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}
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#include <asm/arch/atmel_mpddrc.h>
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static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_13 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
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ddr2->rtr = 0x411;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct atmel_mpddrc_config ddr2;
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unsigned long csa;
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(AT91_PMC_DDR, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
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csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
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csa |= AT91_MATRIX_EBI_DBPD_OFF;
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csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
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writel(csa, &matrix->ebicsa);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
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}
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#endif
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