158 lines
3.6 KiB
C
158 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Clock initialization routines
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*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#ifndef __EXYNOS_CLOCK_INIT_H
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#define __EXYNOS_CLOCK_INIT_H
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enum {
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#ifdef CONFIG_EXYNOS5420
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MEM_TIMINGS_MSR_COUNT = 5,
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#else
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MEM_TIMINGS_MSR_COUNT = 4,
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#endif
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};
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/* These are the ratio's for configuring ARM clock */
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struct arm_clk_ratios {
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unsigned arm_freq_mhz; /* Frequency of ARM core in MHz */
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unsigned apll_mdiv;
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unsigned apll_pdiv;
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unsigned apll_sdiv;
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unsigned arm2_ratio;
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unsigned apll_ratio;
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unsigned pclk_dbg_ratio;
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unsigned atb_ratio;
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unsigned periph_ratio;
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unsigned acp_ratio;
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unsigned cpud_ratio;
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unsigned arm_ratio;
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};
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/* These are the memory timings for a particular memory type and speed */
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struct mem_timings {
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enum mem_manuf mem_manuf; /* Memory manufacturer */
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enum ddr_mode mem_type; /* Memory type */
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unsigned frequency_mhz; /* Frequency of memory in MHz */
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/* Here follow the timing parameters for the selected memory */
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unsigned apll_mdiv;
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unsigned apll_pdiv;
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unsigned apll_sdiv;
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unsigned mpll_mdiv;
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unsigned mpll_pdiv;
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unsigned mpll_sdiv;
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unsigned cpll_mdiv;
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unsigned cpll_pdiv;
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unsigned cpll_sdiv;
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unsigned gpll_mdiv;
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unsigned gpll_pdiv;
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unsigned gpll_sdiv;
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unsigned epll_mdiv;
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unsigned epll_pdiv;
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unsigned epll_sdiv;
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unsigned vpll_mdiv;
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unsigned vpll_pdiv;
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unsigned vpll_sdiv;
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unsigned bpll_mdiv;
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unsigned bpll_pdiv;
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unsigned bpll_sdiv;
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unsigned kpll_mdiv;
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unsigned kpll_pdiv;
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unsigned kpll_sdiv;
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unsigned dpll_mdiv;
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unsigned dpll_pdiv;
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unsigned dpll_sdiv;
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unsigned ipll_mdiv;
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unsigned ipll_pdiv;
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unsigned ipll_sdiv;
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unsigned spll_mdiv;
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unsigned spll_pdiv;
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unsigned spll_sdiv;
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unsigned rpll_mdiv;
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unsigned rpll_pdiv;
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unsigned rpll_sdiv;
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unsigned pclk_cdrex_ratio;
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unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
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unsigned timing_ref;
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unsigned timing_row;
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unsigned timing_data;
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unsigned timing_power;
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/* DQS, DQ, DEBUG offsets */
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unsigned phy0_dqs;
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unsigned phy1_dqs;
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unsigned phy0_dq;
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unsigned phy1_dq;
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unsigned phy0_tFS;
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unsigned phy1_tFS;
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unsigned phy0_pulld_dqs;
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unsigned phy1_pulld_dqs;
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unsigned lpddr3_ctrl_phy_reset;
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unsigned ctrl_start_point;
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unsigned ctrl_inc;
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unsigned ctrl_start;
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unsigned ctrl_dll_on;
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unsigned ctrl_ref;
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unsigned ctrl_force;
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unsigned ctrl_rdlat;
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unsigned ctrl_bstlen;
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unsigned fp_resync;
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unsigned iv_size;
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unsigned dfi_init_start;
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unsigned aref_en;
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unsigned rd_fetch;
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unsigned zq_mode_dds;
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unsigned zq_mode_term;
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unsigned zq_mode_noterm; /* 1 to allow termination disable */
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unsigned memcontrol;
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unsigned memconfig;
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unsigned membaseconfig0;
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unsigned membaseconfig1;
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unsigned prechconfig_tp_cnt;
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unsigned dpwrdn_cyc;
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unsigned dsref_cyc;
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unsigned concontrol;
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/* Channel and Chip Selection */
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uint8_t dmc_channels; /* number of memory channels */
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uint8_t chips_per_channel; /* number of chips per channel */
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uint8_t chips_to_configure; /* number of chips to configure */
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uint8_t send_zq_init; /* 1 to send this command */
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unsigned impedance; /* drive strength impedeance */
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uint8_t gate_leveling_enable; /* check gate leveling is enabled */
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uint8_t read_leveling_enable; /* check h/w read leveling is enabled */
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};
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/**
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* Get the correct memory timings for our selected memory type and speed.
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*
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* This function can be called from SPL or the main U-Boot.
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*
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* @return pointer to the memory timings that we should use
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*/
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struct mem_timings *clock_get_mem_timings(void);
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/*
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* Initialize clock for the device
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*/
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void system_clock_init(void);
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/*
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* Set clock divisor value for booting from EMMC.
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*/
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void emmc_boot_clk_div_set(void);
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#endif
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