56 lines
1.3 KiB
Plaintext
Executable File
56 lines
1.3 KiB
Plaintext
Executable File
Novatek IVOT Platforms Device Tree Bindings
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-------------------------------------------------
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!!!!!Do not edit this dtsi file!!!!!
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* CPU
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Properties:
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- compatible : Should at least contain "cortex-a9".
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- clock-frequency : To delcare the cpu frequency. This value should be synchronized with loader info.
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- cpu-release-addr : SMP will use this address to release the pen
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- next-level-cache : Assign to PL310 L2 outer cache phandle pointer
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* Timer
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We used the cpu core timer and peripheral timer clock info as the following compatible definitions.
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Properties:
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- compatible : Should at least contain "periph_clk". It will be used as cpu timer
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- compatible : Should at least contain "core_clk".
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* gic
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Properties:
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- compatible : Should at least contain "cortex-a7-gic".
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- reg : GIC register info
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- interrupts : Maintenence IRQ
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* pmu
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Properties:
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- compatible : Should at least contain "cortex-a9-pmu". HW PMU to monitor the system performance.
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- interrupt-affinity : CPU core affinity number.
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- interrupts : Fill the SPI IRQ number
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* Cache
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ARM CA9 had an outer cache controller which is named PL310, the following will config related parameters.
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- compatible : Should at least contain "pl310-cache".
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- arm,data-latency: The L2 cache data latency config
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- arm,tag-latency: The L2 cache tag latency config
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