464 lines
15 KiB
C
Executable File
464 lines
15 KiB
C
Executable File
/**
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Header file of SPI module driver
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This file is the header file of SPI module
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@file SPI.h
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@ingroup mIDrvIO_SPI
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2014. All rights reserved.
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*/
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#ifndef _SPI_H
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#define _SPI_H
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#include <kwrap/nvt_type.h>
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/**
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@addtogroup mIDrvIO_SPI
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*/
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//@{
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/**
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SPI ID
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*/
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typedef enum {
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SPI_ID_1, ///< SPI 1 (PIO, DMA)
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SPI_ID_2, ///< SPI 2 (PIO, DMA)
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SPI_ID_3, ///< SPI 3 (PIO, Gyro)
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SPI_ID_4, ///< SPI 4 (PIO, DMA)
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SPI_ID_5, ///< SPI 5 (PIO, DMA)
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SPI_ID_COUNT, ///< SPI ID count
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ENUM_DUMMY4WORD(SPI_ID)
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} SPI_ID;
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/**
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SPI IO CONTROL ID
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*/
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typedef enum {
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ENUM_DUMMY4WORD(SPI_IOCTRL)
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} SPI_IOCTRL;
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/**
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SPI Configuration Identifier
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@note For spi_setConfig()
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*/
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typedef enum {
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SPI_CONFIG_ID_BUSMODE, ///< SPI Bus Mode. Context can be:
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///< - @b SPI_MODE_0 (default)
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///< - @b SPI_MODE_1
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///< - @b SPI_MODE_2
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///< - @b SPI_MODE_3
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SPI_CONFIG_ID_FREQ, ///< SPI Bus Frequency. Unit: Hz (default: 24000000)
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SPI_CONFIG_ID_MSB_LSB, ///< SPI MSB/LSB select. Context can be:
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///< - @b SPI_MSB: MSB (bit) first
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///< - @b SPI_LSB: LSB (bit) first (default)
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SPI_CONFIG_ID_WIDE_BUS_ORDER, ///< Bit order in wide bus mode. Context can be:
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///< - @b SPI_WIDE_BUS_ORDER_NORMAL: normal order (default)
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///< - @b SPI_WIDE_BUS_ORDER_INVERT: inverted order
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SPI_CONFIG_ID_CS_ACT_LEVEL, ///< CS active level select. Context can be:
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///< - @b SPI_CS_ACT_LEVEL_LOW: low active (default)
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///< - @b SPI_CS_ACT_LEVEL_HIGH: high active
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SPI_CONFIG_ID_CS_CK_DLY, ///< CS edge to Clock edge delay. unit: us
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SPI_CONFIG_ID_PKT_DLY, ///< Delay between each SPI packet. Default 0 us. unit: us.
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SPI_CONFIG_ID_RDY_POLARITY, ///< Polarity of SPI_RDY (only SPI_ID_4 support SPI_RDY PIN)
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///< - @b SPI_RDY_ACT_LEVEL_LOW: low ready (default)
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///< - @b SPI_RDY_ACT_LEVEL_HIGH: high ready
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SPI_CONFIG_ID_DO_HZ_EN, ///< SPI DO output Hi-Z control
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///< - @b TRUE: SPI DO be hi-Z when no data is needed to output
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///< - @b FALSE: SPI DO will be driven by SPI controller event no data is needed to output (default)
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SPI_CONFIG_ID_AUTOPINMUX, ///< SPI auto pinmux control (NOT support)
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///< - @b TRUE: SPI will enable pinmux (according to pinmux_init()) when spi_open(), disable pinmux when spi_close()
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///< - @b FALSE: SPI driver will not alter pinmux(default)
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SPI_CONFIG_ID_VD_SRC, ///< SPI Gyro VD source select
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///< - @b SPI_VD_SRC_SIE1: SIE1 (default)
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///< - @b SPI_VD_SRC_SIE2: SIE2
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SPI_CONFIG_ID_LATCH_CLK_SHIFT, ///< Shift latch clock.
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///< Data is from SPI_CONFIG_ID_LATCH_CLK_EDGE
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///< - @b SPI_LATCH_CLK_0T (default)
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///< - @b SPI_LATCH_CLK_1T
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///< - @b SPI_LATCH_CLK_2T
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SPI_CONFIG_ID_LATCH_CLK_EDGE, ///< Latch clock edge
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///< Latch data from SPI_CONFIG_ID_LATCH_DATA_SRC
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///< - @b SPI_LATCH_EDGE_RISING (default)
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///< - @b SPI_LATCH_EDGE_FALLING
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SPI_CONFIG_ID_LATCH_DATA_SRC, ///< Latch Data source
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///< - @b SPI_LATCH_DATA_PAD (default)
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///< - @b SPI_LATCH_DATA_DLY (data from SPI_CONFIG_ID_DELAY_CLK_EDGE)
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SPI_CONFIG_ID_DELAY_CLK_EDGE, ///< Delay chain clock edge select
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///< (Clock is from SPI_CONFIG_ID_DELAY_CHAIN_SEL)
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///< - @b SPI_DLY_CLK_EDGE_RISING (default)
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///< - @b SPI_DLY_CLK_EDGE_FALLING
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SPI_CONFIG_ID_DELAY_CHAIN_SEL, ///< Delay chain select (unit: delay cell)
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///< (Clock is from SPI_CONFIG_ID_DELAY_CLK_POLARITY)
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///< (Default value: 0)
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///< (range: 0 ~ 63)
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SPI_CONFIG_ID_DELAY_CLK_POLARITY,///< Delay clock polarity
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///< (Clock is from SPI_CONFIG_ID_DELAY_CLK_SRC)
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///< - @b SPI_DLY_CLK_POLARITY_NORMAL (default)
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///< - @b SPI_DLY_CLK_POLARITY_INVERT
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SPI_CONFIG_ID_DELAY_CLK_SRC, ///< Delay chain clock source
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///< - @b SPI_DLY_CLK_SRC_INTERNAL (default)
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///< - @b SPI_DLY_CLK_SRC_PAD
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SPI_CONFIG_ID_GYRO_SYNC_END_OFFSET, ///< Adjust offset of SPI_GYRO_INT_SYNC_END
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///< (unit: gyro gransfer)
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///< (range: 0 ~ SPI_GYRO_INFO.uiTransferCount - 1, where SPI_GYRO_INFO is your object for spi_startGyro())
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///< - @b 0: Issue SPI_GYRO_INT_SYNC_END at last gyro gransfer (default)
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///< - @b 1: Issue SPI_GYRO_INT_SYNC_END at second-last gyro gransfer
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///< - @b 2: Issue SPI_GYRO_INT_SYNC_END at third-last gyro gransfer
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///< - etc...
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////////// Engineering Usage ///////////////////
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SPI_CONFIG_ID_ENG_PKT_COUNT, //< engineer mode: packet count for spi_writeSingle(), spi_readSingle(), spi_writeReadSingle().
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//< Context can be:
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//< - @b 1: 1 packet
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//< - @b 2: 2 packet
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//< - @b 4: 4 packet
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SPI_CONFIG_ID_ENG_MSB_LSB, //< engineer mode: MSB/LSB. Context can be:
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//< - @b SPI_MSB: MSB (bit) first
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//< - @b SPI_LSB: LSB (bit) first
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SPI_CONFIG_ID_ENG_DMA_ABORT, //< engineer mode: DMA abort. Context can be:
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//< - @b FALSE: no DMA abort after DMA is triggered
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//< - @b TRUE: test DMA abort after DMA is triggered
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SPI_CONFIG_ID_ENG_GYRO_UNIT, //< engineer mode: gyro delay unit. Context can be:
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//< - @b FALSE: unit is us (default value)
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//< - @b TRUE: unit is SPI CLK
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SPI_CONFIG_ID_ENG_GYRO_INTMSK, //< engineer mode: gyro interrupt mask
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ENUM_DUMMY4WORD(SPI_CONFIG_ID)
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} SPI_CONFIG_ID;
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/**
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SPI mode
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_BUSMODE, )
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*/
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typedef enum {
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SPI_MODE_0, ///< MODE 0
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SPI_MODE_1, ///< MODE 1
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SPI_MODE_2, ///< MODE 2
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SPI_MODE_3, ///< MODE 3
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ENUM_DUMMY4WORD(SPI_MODE)
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} SPI_MODE;
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/**
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SPI LSB/MSB select
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_MSB_LSB, )
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*/
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typedef enum {
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SPI_MSB, ///< MSb first
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SPI_LSB, ///< LSb first
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ENUM_DUMMY4WORD(SPI_LSB_MSB)
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} SPI_LSB_MSB;
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/**
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SPI CS active level
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_CS_ACT_LEVEL, )
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*/
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typedef enum {
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SPI_CS_ACT_LEVEL_LOW, ///< CS is low active
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SPI_CS_ACT_LEVEL_HIGH, ///< CS is high active
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ENUM_DUMMY4WORD(SPI_CS_ACT_LEVEL)
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} SPI_CS_ACT_LEVEL;
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/**
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SPI RDY active level
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_RDY_POLARITY, )
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*/
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typedef enum {
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SPI_RDY_ACT_LEVEL_LOW, ///< SPI_RDY is low ready (i.e. high busy)
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SPI_RDY_ACT_LEVEL_HIGH, ///< SPI_RDY is high ready (i.e. low busy)
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ENUM_DUMMY4WORD(SPI_RDY_ACT_LEVEL)
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} SPI_RDY_ACT_LEVEL;
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/*
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SPI bus width
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@note For spi_setBusWidth()
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*/
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typedef enum {
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SPI_BUS_WIDTH_1_BIT, //< Bus width is 1 bit (full duplex)
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SPI_BUS_WIDTH_2_BITS, //< Bus width is 2 bits (half duplex)
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// SPI_BUS_WIDTH_4_BITS, //< Bus width is 4 bits (half duplex)
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SPI_BUS_WIDTH_HD_1BIT, //< Bus width is half duplex 1 bit (only require CS, CLK, DIO)
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ENUM_DUMMY4WORD(SPI_BUS_WIDTH)
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} SPI_BUS_WIDTH;
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/**
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SPI wide bus order
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_WIDE_BUS_ORDER, )
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*/
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typedef enum {
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SPI_WIDE_BUS_ORDER_NORMAL, ///< Normal order. Transmit sequence is SPI_IO3, SPI_IO2, SPI_IO1, SPI_IO0.
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SPI_WIDE_BUS_ORDER_INVERT, ///< Invert order. Transmit sequence is SPI_IO0, SPI_IO1, SPI_IO2, SPI_IO3.
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ENUM_DUMMY4WORD(SPI_WIDE_BUS_ORDER)
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} SPI_WIDE_BUS_ORDER;
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/**
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SPI transfer length
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@note For spi_setTransferLen()
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*/
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typedef enum {
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SPI_TRANSFER_LEN_1BYTE, ///< 1 byte
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SPI_TRANSFER_LEN_2BYTES, ///< 2 bytes
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ENUM_DUMMY4WORD(SPI_TRANSFER_LEN)
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} SPI_TRANSFER_LEN;
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/**
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SPI latch clock
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_LATCH_CLK_SHIFT, )
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*/
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typedef enum {
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SPI_LATCH_CLK_0T, ///< Latch at 0T
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SPI_LATCH_CLK_1T, ///< Latch at 1T
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SPI_LATCH_CLK_2T, ///< Latch at 2T
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ENUM_DUMMY4WORD(SPI_LATCH_CLK)
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} SPI_LATCH_CLK;
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/**
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SPI latch edge
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_LATCH_CLK_EDGE, )
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*/
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typedef enum {
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SPI_LATCH_EDGE_RISING, ///< Latch at rising edge
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SPI_LATCH_EDGE_FALLING, ///< Latch at falling edge
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ENUM_DUMMY4WORD(SPI_LATCH_EDGE)
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} SPI_LATCH_EDGE;
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/**
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SPI latch data source
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_LATCH_DATA_SRC, )
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*/
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typedef enum {
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SPI_LATCH_DATA_PAD, ///< Latch data from data PAD
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SPI_LATCH_DATA_DLY, ///< Latch data from result of delay chain
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ENUM_DUMMY4WORD(SPI_LATCH_DATA)
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} SPI_LATCH_DATA;
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/**
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SPI delay clock edge
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Select to use rising or falling edge of clock output by delay chain
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_DELAY_CLK_EDGE, )
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*/
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typedef enum {
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SPI_DLY_CLK_EDGE_RISING, ///< Sample data at rising edge
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SPI_DLY_CLK_EDGE_FALLING, ///< Sample data at falling edge
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ENUM_DUMMY4WORD(SPI_DLY_CLK_EDGE)
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} SPI_DLY_CLK_EDGE;
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/**
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SPI delay clock polarity
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Select to select polarity (normal/invert) of delay chain input clock
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_DELAY_CLK_POLARITY, )
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*/
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typedef enum {
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SPI_DLY_CLK_POLARITY_NORMAL, ///< Normal
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SPI_DLY_CLK_POLARITY_INVERT, ///< Invert
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ENUM_DUMMY4WORD(SPI_DLY_CLK_POLARITY)
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} SPI_DLY_CLK_POLARITY;
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/**
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SPI delay clock source
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Select clock to be delayed by delay chain
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@note For spi_setConfig(SPI_ID, SPI_CONFIG_ID_DELAY_CLK_SRC, )
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*/
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typedef enum {
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SPI_DLY_CLK_SRC_INTERNAL, ///< Delay internal SPI clock
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SPI_DLY_CLK_SRC_PAD, ///< Delay SPI clock from SPI_CLK PAD
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ENUM_DUMMY4WORD(SPI_DLY_CLK_SRC)
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} SPI_DLY_CLK_SRC;
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/**
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SPI gyro mode
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@note For gyroMode of SPI_GYRO_INFO
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*/
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typedef enum {
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SPI_GYRO_MODE_SIE_SYNC, ///< SIE sync mode
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SPI_GYRO_MODE_ONE_SHOT, ///< one shot mode
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SPI_GYRO_MODE_FREE_RUN, ///< free run mode
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SPI_GYRO_MODE_SIE_SYNC_WITH_RDY, ///< SIE sync mode with ready PIN from device
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ENUM_DUMMY4WORD(SPI_GYRO_MODE)
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} SPI_GYRO_MODE;
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/**
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SPI GYRO interrupt
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@note For uiGyroSts of SPI_GYRO_CB
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*/
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typedef enum {
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SPI_GYRO_INT_SYNC_END = 0x00000001, ///< End of one SIE sync. All data in this sync are completed.
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SPI_GYRO_INT_OVERRUN = 0x00000002, ///< HW FIFO overrun. FW should do error handling, ex: re-start gyro polling
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SPI_GYRO_INT_SEQ_ERR = 0x00000004, ///< Sequence error. Next SIE sync is too early.
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SPI_GYRO_INT_TRS_TIMEOUT = 0x00000008, ///< A Gyro Transfer timeout. (Maybe SPI_RDY hold by device too long)
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SPI_GYRO_INT_CHANGE_END = 0x00000010, ///< End of SIE VD after spi_changeGyro() is invoked. (Next VD will be new gyro setting)
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SPI_GYRO_INT_LAST_TRS = 0x00000020, ///< End of last transfer in a VD period
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SPI_GYRO_INT_QUEUE_THRESHOLD = 0x00000100, ///< SW Queue exceed threshold. Upper layer should sink Gyro data ASAP.
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SPI_GYRO_INT_QUEUE_OVERRUN = 0x00000200, ///< Sw Queue overrun. FW should do error handling.
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ENUM_DUMMY4WORD(SPI_GYRO_INT)
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} SPI_GYRO_INT;
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/**
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SPI VD source
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@note For SPI_CONFIG_ID_VD_SRC
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*/
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typedef enum {
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SPI_VD_SRC_SIE1, ///< VD source is SIE1
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SPI_VD_SRC_SIE2, ///< VD source is SIE2
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SPI_VD_SRC_SIE4, ///< VD source is SIE4
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SPI_VD_SRC_SIE5, ///< VD source is SIE5
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ENUM_DUMMY4WORD(SPI_VD_SRC)
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} SPI_VD_SRC;
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/*
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SPI initialization infomation
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(OBSOLETE structure)
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*/
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typedef struct {
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BOOL bCSActiveLow; ///< CS polarity
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///< - TRUE: CS is active LOW
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///< - FALSE: CS is active HIGH
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BOOL bMasterMode; ///< Master mode
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///< - TRUE: master mode
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UINT32 uiFreq; ///< Clock frequency (unit: Hz)
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SPI_MODE spiMODE; ///< SPI MODE select
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///< - SPI_MODE_0: mode 0
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///< - SPI_MODE_1: mode 1
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///< - SPI_MODE_2: mode 2
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///< - SPI_MODE_3: mode 3
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BOOL bLSB; ///< LSB mode select (bit order)
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///< - TRUE: LSB mode
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///< - FALSE: MSB mode
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SPI_WIDE_BUS_ORDER wideBusOrder; ///< Bus order is wide bus mode (SPI_BUS_WIDTH_2_BITS)
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///< - SPI_WIDE_BUS_ORDER_NORMAL: normal order
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///< - SPI_WIDE_BUS_ORDER_INVERT: inverted order
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UINT32 uiCsCkDelay; ///< Delay time between CS edge and first clock edge
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UINT32 uiPktDelay; ///< Delay time between each SPI packet
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} SPI_INIT_INFO, *PSPI_INIT_INFO;
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/**
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GYRO Buffer Queue
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@note For spi_getGyroData()
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*/
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typedef struct {
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UINT32 uiFrameID; ///< record frame ID of this buffer
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UINT32 uiDataID; ///< record Gyro data ID. Valid value: 0~31
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UINT32 vRecvWord[2]; ///< stores data received in one Gyro data transfer
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} GYRO_BUF_QUEUE, *PGYRO_BUF_QUEUE;
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/**
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@name SPI gyro mode call back prototype
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@note For pEventHandler of SPI_GYRO_INFO
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@param[in] gyroSts gyro status. Can be:
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- @b SPI_GYRO_INT_SYNC_END
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- @b SPI_GYRO_INT_OVERRUN
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- @b SPI_GYRO_INT_SEQ_ERR
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- @b SPI_GYRO_INT_TRS_TIMEOUT
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@return void
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*/
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//@{
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typedef void (*SPI_GYRO_CB)(SPI_GYRO_INT gyroSts);
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//@}
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/**
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SPI GYRO control infomation
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@note For spi_startGyro()
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*/
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typedef struct {
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SPI_GYRO_MODE gyroMode; ///< Gyro trigger mode
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UINT32 uiOpInterval; ///< Delay between 2 OP (unit: us)
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UINT32 uiTransferInterval; ///< Delay between 2 transfer (unit: us)
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UINT32 uiTransferCount; ///< total transfer in single run. valid value: 1~32
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UINT32 uiTransferLen; ///< length of Transer: unit: OP. valid value: 1~4
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UINT32 uiOp0Length; ///< length of OP0. unit: byte. valid value: 1~8
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UINT32 uiOp1Length; ///< length of OP1. unit: byte. valid value: 1~8
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UINT32 uiOp2Length; ///< length of OP2. unit: byte. valid value: 1~8
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UINT32 uiOp3Length; ///< length of OP3. unit: byte. valid value: 1~8
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UINT8 vOp0OutData[8]; ///< stores data to be output in OP0
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UINT8 vOp1OutData[8]; ///< stores data to be output in OP1
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UINT8 vOp2OutData[8]; ///< stores data to be output in OP2
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UINT8 vOp3OutData[8]; ///< stores data to be output in OP3
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void (*pEventHandler)(SPI_GYRO_INT gyroSts); ///< EventHandler function pointer, set to NULL if you don't want to handle audio event
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} SPI_GYRO_INFO, *PSPI_GYRO_INFO;
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extern ER spi_open(SPI_ID spiID);
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extern ER spi_close(SPI_ID spiID);
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extern BOOL spi_isOpened(SPI_ID spiID);
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extern ER spi_setTransferLen(SPI_ID spiID, SPI_TRANSFER_LEN length);
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extern void spi_setCSActive(SPI_ID spiID, BOOL bCSActive);
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extern ER spi_writeReadData(SPI_ID spiID, UINT32 uiWordCount, UINT32 *pTxBuf, UINT32 *pRxBuf, BOOL bDmaMode);
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extern ER spi_waitDataDone(SPI_ID spiID);
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extern ER spi_writeSingle(SPI_ID spiID, UINT32 uiTxWord);
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extern ER spi_writePacket(SPI_ID spiID, UINT32 uiPktCnt, UINT32 uiTxWord);
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extern ER spi_readSingle(SPI_ID spiID, UINT32 *pRxWord);
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extern ER spi_writeReadSingle(SPI_ID spiID, UINT32 uiTxWord, UINT32 *pRxWord);
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extern ER spi_startGyro(SPI_ID spiID, SPI_GYRO_INFO *pGyroInfo);
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extern ER spi_changeGyro(SPI_ID spiID, SPI_GYRO_INFO *pGyroInfo, UINT32 uiSyncEndOffset);
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extern ER spi_stopGyro(SPI_ID spiID);
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extern UINT32 spi_getGyroQueueCount(SPI_ID spiID);
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extern ER spi_getGyroData(SPI_ID spiID, PGYRO_BUF_QUEUE pGyroData);
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extern ER spi_setConfig(SPI_ID spiID, SPI_CONFIG_ID configID, UINT32 configContext);
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extern ER spi_enBitMatch(SPI_ID spiID, UINT32 uiCmd, UINT32 uiBitPosition, BOOL bWaitValue);
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extern ER spi_waitBitMatch(SPI_ID spiID, UINT32 uiTimeoutMs);
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extern ER spi_setBusWidth(SPI_ID spiID, SPI_BUS_WIDTH busWidth);
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extern void spi_platform_init(void);
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extern void spi_platform_uninit(void);
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//@}
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#endif
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