167 lines
3.6 KiB
C
167 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Stout board CPLD access support
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*
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* Copyright (C) 2015 Renesas Electronics Europe GmbH
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* Copyright (C) 2015 Renesas Electronics Corporation
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* Copyright (C) 2015 Cogent Embedded, Inc.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include "cpld.h"
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#define SCLK (92 + 24)
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#define SSTBZ (92 + 25)
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#define MOSI (92 + 26)
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#define MISO (92 + 27)
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#define CPLD_ADDR_MODE 0x00 /* RW */
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#define CPLD_ADDR_MUX 0x01 /* RW */
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#define CPLD_ADDR_HDMI 0x02 /* RW */
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#define CPLD_ADDR_DIPSW 0x08 /* R */
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#define CPLD_ADDR_RESET 0x80 /* RW */
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#define CPLD_ADDR_VERSION 0xFF /* R */
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static u32 cpld_read(u8 addr)
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{
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int i;
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u32 data = 0;
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for (i = 0; i < 8; i++) {
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */
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gpio_set_value(SCLK, 1);
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addr <<= 1;
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gpio_set_value(SCLK, 0);
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}
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gpio_set_value(MOSI, 0); /* READ */
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gpio_set_value(SSTBZ, 0);
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gpio_set_value(SCLK, 1);
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gpio_set_value(SCLK, 0);
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gpio_set_value(SSTBZ, 1);
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for (i = 0; i < 32; i++) {
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gpio_set_value(SCLK, 1);
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data <<= 1;
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data |= gpio_get_value(MISO); /* MSB first */
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gpio_set_value(SCLK, 0);
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}
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return data;
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}
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static void cpld_write(u8 addr, u32 data)
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{
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int i;
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for (i = 0; i < 32; i++) {
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gpio_set_value(MOSI, data & (1 << 31)); /* MSB first */
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gpio_set_value(SCLK, 1);
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data <<= 1;
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gpio_set_value(SCLK, 0);
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}
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for (i = 0; i < 8; i++) {
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gpio_set_value(MOSI, addr & 0x80); /* MSB first */
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gpio_set_value(SCLK, 1);
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addr <<= 1;
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gpio_set_value(SCLK, 0);
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}
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gpio_set_value(MOSI, 1); /* WRITE */
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gpio_set_value(SSTBZ, 0);
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gpio_set_value(SCLK, 1);
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gpio_set_value(SCLK, 0);
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gpio_set_value(SSTBZ, 1);
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}
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/* LSI pin pull-up control */
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#define PUPR3 0xe606010C
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#define PUPR3_SD3_DAT1 (1 << 27)
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void cpld_init(void)
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{
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u32 val;
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/* PULL-UP on MISO line */
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val = readl(PUPR3);
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val |= PUPR3_SD3_DAT1;
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writel(val, PUPR3);
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gpio_request(SCLK, "SCLK");
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gpio_request(SSTBZ, "SSTBZ");
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gpio_request(MOSI, "MOSI");
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gpio_request(MISO, "MISO");
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gpio_direction_output(SCLK, 0);
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gpio_direction_output(SSTBZ, 1);
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gpio_direction_output(MOSI, 0);
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gpio_direction_input(MISO);
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/* dummy read */
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cpld_read(CPLD_ADDR_VERSION);
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printf("CPLD version: 0x%08x\n",
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cpld_read(CPLD_ADDR_VERSION));
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printf("H2 Mode setting (MD0..28): 0x%08x\n",
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cpld_read(CPLD_ADDR_MODE));
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printf("Multiplexer settings: 0x%08x\n",
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cpld_read(CPLD_ADDR_MUX));
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printf("HDMI setting: 0x%08x\n",
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cpld_read(CPLD_ADDR_HDMI));
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printf("DIPSW (SW3): 0x%08x\n",
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cpld_read(CPLD_ADDR_DIPSW));
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#ifdef CONFIG_SH_SDHI
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/* switch MUX to SD0 */
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val = cpld_read(CPLD_ADDR_MUX);
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val &= ~MUX_MSK_SD0;
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val |= MUX_VAL_SD0;
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cpld_write(CPLD_ADDR_MUX, val);
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#endif
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}
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static int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 addr, val;
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if (argc < 3)
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return CMD_RET_USAGE;
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addr = simple_strtoul(argv[2], NULL, 16);
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if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
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addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_HDMI ||
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addr == CPLD_ADDR_DIPSW || addr == CPLD_ADDR_RESET)) {
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printf("cpld invalid addr\n");
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return CMD_RET_USAGE;
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}
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if (argc == 3 && strcmp(argv[1], "read") == 0) {
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printf("0x%x\n", cpld_read(addr));
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} else if (argc == 4 && strcmp(argv[1], "write") == 0) {
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val = simple_strtoul(argv[3], NULL, 16);
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if (addr == CPLD_ADDR_MUX) {
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/* never mask SCIFA0 console */
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val &= ~MUX_MSK_SCIFA0_USB;
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val |= MUX_VAL_SCIFA0_USB;
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}
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cpld_write(addr, val);
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}
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return 0;
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}
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U_BOOT_CMD(
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cpld, 4, 1, do_cpld,
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"CPLD access",
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"read addr\n"
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"cpld write addr val\n"
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);
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void reset_cpu(ulong addr)
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{
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cpld_write(CPLD_ADDR_RESET, 1);
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}
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