173 lines
5.2 KiB
C
173 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION.
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <linux/sizes.h>
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#include <asm/arch/tegra.h>
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#include <asm/armv8/mmu.h>
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/*
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* Size of a region that's large enough to hold the relocated U-Boot and all
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* other allocations made around it (stack, heap, page tables, etc.)
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* In practice, running "bdinfo" at the shell prompt, the stack reaches about
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* 5MB from the address selected for ram_top as of the time of writing,
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* so a 16MB region should be plenty.
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*/
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#define MIN_USABLE_RAM_SIZE SZ_16M
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/*
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* The amount of space we expect to require for stack usage. Used to validate
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* that all reservations fit into the region selected for the relocation target
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*/
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#define MIN_USABLE_STACK_SIZE SZ_1M
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DECLARE_GLOBAL_DATA_PTR;
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extern unsigned long nvtboot_boot_x0;
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extern struct mm_region tegra_mem_map[];
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/*
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* These variables are written to before relocation, and hence cannot be
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* in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
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* The section attribute forces this into .data and avoids this issue. This
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* also has the nice side-effect of the content being valid after relocation.
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*/
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/* The number of valid entries in ram_banks[] */
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static int ram_bank_count __attribute__((section(".data")));
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/*
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* The usable top-of-RAM for U-Boot. This is both:
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* a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
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* b) At the end of a region that has enough space to hold the relocated U-Boot
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* and all other allocations made around it (stack, heap, page tables, etc.)
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*/
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static u64 ram_top __attribute__((section(".data")));
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/* The base address of the region of RAM that ends at ram_top */
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static u64 region_base __attribute__((section(".data")));
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int dram_init(void)
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{
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unsigned int na, ns;
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const void *nvtboot_blob = (void *)nvtboot_boot_x0;
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int node, len, i;
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const u32 *prop;
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na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
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ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
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node = fdt_path_offset(nvtboot_blob, "/memory");
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if (node < 0) {
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pr_err("Can't find /memory node in nvtboot DTB");
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hang();
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}
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prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
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if (!prop) {
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pr_err("Can't find /memory/reg property in nvtboot DTB");
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hang();
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}
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/* Calculate the true # of base/size pairs to read */
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len /= 4; /* Convert bytes to number of cells */
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len /= (na + ns); /* Convert cells to number of banks */
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if (len > CONFIG_NR_DRAM_BANKS)
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len = CONFIG_NR_DRAM_BANKS;
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/* Parse the /memory node, and save useful entries */
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gd->ram_size = 0;
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ram_bank_count = 0;
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for (i = 0; i < len; i++) {
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u64 bank_start, bank_end, bank_size, usable_bank_size;
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/* Extract raw memory region data from DTB */
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bank_start = fdt_read_number(prop, na);
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prop += na;
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bank_size = fdt_read_number(prop, ns);
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prop += ns;
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gd->ram_size += bank_size;
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bank_end = bank_start + bank_size;
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debug("Bank %d: %llx..%llx (+%llx)\n", i,
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bank_start, bank_end, bank_size);
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/*
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* Align the bank to MMU section size. This is not strictly
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* necessary, since the translation table construction code
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* handles page granularity without issue. However, aligning
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* the MMU entries reduces the size and number of levels in the
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* page table, so is worth it.
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*/
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bank_start = ROUND(bank_start, SZ_2M);
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bank_end = bank_end & ~(SZ_2M - 1);
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bank_size = bank_end - bank_start;
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debug(" aligned: %llx..%llx (+%llx)\n",
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bank_start, bank_end, bank_size);
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if (bank_end <= bank_start)
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continue;
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/* Record data used to create MMU translation tables */
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ram_bank_count++;
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/* Index below is deliberately 1-based to skip MMIO entry */
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tegra_mem_map[ram_bank_count].virt = bank_start;
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tegra_mem_map[ram_bank_count].phys = bank_start;
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tegra_mem_map[ram_bank_count].size = bank_size;
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tegra_mem_map[ram_bank_count].attrs =
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PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
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/* Determine best bank to relocate U-Boot into */
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if (bank_end > SZ_4G)
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bank_end = SZ_4G;
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debug(" end %llx (usable)\n", bank_end);
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usable_bank_size = bank_end - bank_start;
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debug(" size %llx (usable)\n", usable_bank_size);
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if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
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(bank_end > ram_top)) {
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ram_top = bank_end;
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region_base = bank_start;
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debug("ram top now %llx\n", ram_top);
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}
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}
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/* Ensure memory map contains the desired sentinel entry */
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tegra_mem_map[ram_bank_count + 1].virt = 0;
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tegra_mem_map[ram_bank_count + 1].phys = 0;
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tegra_mem_map[ram_bank_count + 1].size = 0;
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tegra_mem_map[ram_bank_count + 1].attrs = 0;
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/* Error out if a relocation target couldn't be found */
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if (!ram_top) {
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pr_err("Can't find a usable RAM top");
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hang();
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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int i;
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if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
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pr_err("Reservations exceed chosen region size");
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hang();
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}
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for (i = 0; i < ram_bank_count; i++) {
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gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
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gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
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}
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#ifdef CONFIG_PCI
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gd->pci_ram_top = ram_top;
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#endif
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return 0;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return ram_top;
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}
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