536 lines
14 KiB
C
Executable File
536 lines
14 KiB
C
Executable File
/**
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Clock info
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@file clock.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/IOAddress.h>
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#include <asm/arch/hardware.h>
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#include <asm/nvt-common/nvt_types.h>
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#include <asm/nvt-common/nvt_common.h>
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#include <asm/nvt-common/rcw_macro.h>
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#define SYSTEM_CLOCK_RATE_OFS 0x10
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#define CPU_CLOCK_RATE_RATIO0_OFS 0x4820
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#define CPU_CLOCK_RATE_RATIO1_OFS 0x4824
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#define CPU_CLOCK_RATE_RATIO2_OFS 0x4828
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#define DMA_CLOCK_RATE_RATIO0_OFS (0x4000 + 0x4C0 + 0x20)
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#define DMA_CLOCK_RATE_RATIO1_OFS (0x4000 + 0x4C0 + 0x24)
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#define DMA_CLOCK_RATE_RATIO2_OFS (0x4000 + 0x4C0 + 0x28)
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#define PLL_CLKSEL_CPU (0)
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#define PLL_CLKSEL_CPU_80 (0x00 << PLL_CLKSEL_CPU) //< Select CPU clock 80MHz
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#define PLL_CLKSEL_CPU_ARMPLL (0x01 << PLL_CLKSEL_CPU) //< Select CPU clock ARMPLL (for CPU)
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#define PLL_CLKSEL_CPU_480 (0x02 << PLL_CLKSEL_CPU) //< Select CPU clock 480MHz
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#define PLL_CLKSEL_CPUMASK (0x3)
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#ifdef CONFIG_NVT_FPGA_EMULATION
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#define CALCULATE_CPU_FREQ_UNIT_US 100000
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#define timer_gettick() readl(IOADDR_TIMER_REG_BASE + 0x108) * (10)
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#define core_timer_gettick() readl(IOADDR_SYSCNT_READ_BASE +0x00)
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#else
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#define CALCULATE_CPU_FREQ_UNIT_US 100000
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#define timer_gettick() readl(IOADDR_TIMER_REG_BASE + 0x108)
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#define core_timer_gettick() readl(IOADDR_SYSCNT_READ_BASE +0x00)
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#endif
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void core_timer_delay(u32 us);
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u64 ca53_get_cycle_count(void);
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void ca53_cycle_count_stop(void);
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void ca53_cycle_count_start(BOOL do_reset, BOOL enable_divider);
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inline void apll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (APLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 apll_get_data(u8 offset)
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{
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return 0;
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}
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#ifdef CONFIG_NVT_FPGA_EMULATION
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static int nvt_cpu_get_freq_by_core_timer(void)
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{
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u32 freq;
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u32 time_1, time_2, temp, time_interval;
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ca53_cycle_count_start(TRUE, FALSE);
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time_1 = ca53_get_cycle_count();
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core_timer_delay(CALCULATE_CPU_FREQ_UNIT_US);
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time_2 = ca53_get_cycle_count();
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if (time_2 > time_1) {
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time_interval = (time_2 - time_1);
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} else {
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temp = 0xFFFFFFFF - time_1;
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time_interval = temp + time_2;
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}
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freq = (time_interval) / (CALCULATE_CPU_FREQ_UNIT_US);
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ca53_cycle_count_stop();
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return (freq * 1000);
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}
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#endif
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#if 0
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inline void apll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(APLL_PAGE_0_EN, (APLL_PAGE_EN_ADDR));
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} else if (PLL_PAGE_B == page) {
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writel(APLL_PAGE_B_EN, (APLL_PAGE_EN_ADDR));
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} else {
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/* ignore */
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}
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}
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#endif
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inline void mpll_set_data(u8 offset, u8 value)
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{
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#if 0
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writel(value, (MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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inline u32 mpll_get_data(u8 offset)
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{
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return 0;
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#if 0
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return readl((MPLL_BASE_ADDR + (offset * 4)));
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#endif
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}
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#if 0
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inline void mpll_enable(pll_page_t page)
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{
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if (PLL_PAGE_0 == page) {
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writel(MPLL_PAGE_0_EN, (MPLL_PAGE_EN_ADDR));
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} else if (PLL_PAGE_B == page) {
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writel(MPLL_PAGE_B_EN, (MPLL_PAGE_EN_ADDR));
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} else {
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/* ignore */
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}
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}
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#endif
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void set_sys_mpll(unsigned long off, unsigned long val)
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{
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#if 0
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val <<= 17;
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val /= 12;
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mpll_enable(PLL_PAGE_B);
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mpll_set_data((off + 0), ((val >> 0) & 0xff));
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mpll_set_data((off + 1), ((val >> 8) & 0xff));
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mpll_set_data((off + 2), ((val >> 16) & 0xff));
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#endif
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}
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unsigned long get_sys_mpll(unsigned long off)
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{
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#if 0
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unsigned long val;
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mpll_enable(PLL_PAGE_B);
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val = mpll_get_data(off);
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val |= (mpll_get_data((off + 1)) << 8);
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val |= (mpll_get_data((off + 2)) << 16);
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val *= 12;
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val += ((1UL << 17) - 1);
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val >>= 17;
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return val;
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#endif
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return 0;
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}
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void set_cpu_clk(unsigned long freq)
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{
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/* no implement */
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}
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unsigned long get_cpu_clk(void)
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{
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unsigned int cpu_clk_sel = 0;
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#ifndef CONFIG_NVT_FPGA_EMULATION
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unsigned int cpu_freq_ratio;
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unsigned int cpu_freq_ratio0, cpu_freq_ratio1, cpu_freq_ratio2;
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#else
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return nvt_cpu_get_freq_by_core_timer();
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#endif
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cpu_clk_sel = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS) & 0x3;
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if (cpu_clk_sel == 1) {
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#ifdef CONFIG_NVT_FPGA_EMULATION
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return 24000;
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#else
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cpu_freq_ratio0 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO0_OFS);
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cpu_freq_ratio1 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO1_OFS);
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cpu_freq_ratio2 = readl(IOADDR_CG_REG_BASE + \
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CPU_CLOCK_RATE_RATIO2_OFS);
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cpu_freq_ratio = cpu_freq_ratio0 | (cpu_freq_ratio1 << 8) | \
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(cpu_freq_ratio2 << 16);
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cpu_freq_ratio = (cpu_freq_ratio << 3);
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return (12 * cpu_freq_ratio / 131072) * 1000;
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#endif
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} else if (cpu_clk_sel == 2) {
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return 480000;
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} else {
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return 80000;
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}
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}
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#define PERF_DEF_OPTS (1 | 16)
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#define PERF_OPT_RESET_CYCLES (2 | 4)
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#define PERF_OPT_DIV64 (8)
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#define ARMV8_PMCR_MASK 0x3f
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#define ARMV8_PMCR_E (1 << 0) /* Enable all counters */
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#define ARMV8_PMCR_P (1 << 1) /* Reset all counters */
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#define ARMV8_PMCR_C (1 << 2) /* Cycle counter reset */
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#define ARMV8_PMCR_D (1 << 3) /* CCNT counts every 64th cpu cycle */
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#define ARMV8_PMCR_X (1 << 4) /* Export to ETM */
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#define ARMV8_PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
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#define ARMV8_PMCR_LC (1 << 6) /* Cycle Counter 64bit overflow*/
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#define ARMV8_PMCR_N_SHIFT 11 /* Number of counters supported */
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#define ARMV8_PMCR_N_MASK 0x1f
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#define ARMV8_PMUSERENR_EN_EL0 (1 << 0) /* EL0 access enable */
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#define ARMV8_PMUSERENR_CR (1 << 2) /* Cycle counter read enable */
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#define ARMV8_PMUSERENR_ER (1 << 3) /* Event counter read enable */
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static inline u32 armv8pmu_pmcr_read(void)
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{
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u64 val = 0;
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asm volatile("mrs %0, pmcr_el0" : "=r"(val));
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return (u32)val;
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}
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static inline void armv8pmu_pmcr_write(u32 val)
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{
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val &= ARMV8_PMCR_MASK;
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isb();
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asm volatile("msr pmcr_el0, %0" : : "r"((u64)val));
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}
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static inline long long armv8_read_CNTPCT_EL0(void)
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{
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long long val;
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asm volatile("mrs %0, CNTVCT_EL0" : "=r"(val));
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return val;
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}
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static void enable_cpu_counters(void)
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{
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u64 val;
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/* Disable cycle counter overflow interrupt */
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asm volatile("msr pmintenset_el1, %0" : : "r"((u64)(0 << 31)));
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/* Enable cycle counter */
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asm volatile("msr pmcntenset_el0, %0" :: "r" BIT(31));
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/* Enable user-mode access to cycle counters. */
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asm volatile("msr pmuserenr_el0, %0" : : "r"(BIT(0) | BIT(2)));
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/* Clear cycle counter and start */
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asm volatile("mrs %0, pmcr_el0" : "=r"(val));
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val |= (BIT(0) | BIT(2));
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isb();
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asm volatile("msr pmcr_el0, %0" : : "r"(val));
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val = BIT(27);
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asm volatile("msr pmccfiltr_el0, %0" : : "r"(val));
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}
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static void disable_cpu_counters(void)
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{
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/* Disable cycle counter */
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asm volatile("msr pmcntenset_el0, %0" :: "r"(0 << 31));
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/* Disable user-mode access to counters. */
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asm volatile("msr pmuserenr_el0, %0" : : "r"((u64)0));
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}
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static inline u64 arch_counter_get_cntpct(void)
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{
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long long val;
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asm volatile("mrs %0, CNTVCT_EL0" : "=r"(val));
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return val;
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}
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//static BOOL cpu_count_open = FALSE;
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void timer2_delay(u32 us)
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{
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u32 start, end;
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start = timer_gettick();
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/*check timer count to target level*/
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while (1) {
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end = timer_gettick();
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if ((end - start) > us) {
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break;
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}
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}
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}
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void core_timer_delay(u32 us)
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{
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u32 start, end;
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u32 tick;
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u32 total_tick;
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tick = (1000 / (CONFIG_SYS_HZ_CLOCK / 1000000));
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total_tick = us * 1000 / (u32)tick;
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start = core_timer_gettick();
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/*check timer count to target level*/
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while (1) {
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end = core_timer_gettick();
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if ((end - start) > (u32)total_tick) {
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break;
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}
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}
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}
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void ca53_cycle_count_start(BOOL do_reset, BOOL enable_divider)
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{
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enable_cpu_counters();
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return;
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}
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/**
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CA53 get CPU clock cycle count
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get CPU clock cycle count
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@param[out] type
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@return success or not
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- @b UINT64: clock cycle of CPU
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*/
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u64 ca53_get_cycle_count(void)
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{
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u64 cval;
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isb();
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asm volatile("mrs %0, PMCCNTR_EL0" : "=r"(cval));
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return cval;
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}
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void ca53_cycle_count_stop(void)
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{
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disable_cpu_counters();
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return;
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}
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int do_nvt_cpu_get_freq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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u64 time_1, time_2, temp, time_interval;
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u32 freq;
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u32 fpga = 0;
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if (!strncmp(argv[1], "fpga", 4)) {
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fpga = 1;
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} else if (!strncmp(argv[1], "help", 4)) {
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return CMD_RET_USAGE;
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}
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ca53_cycle_count_start(TRUE, FALSE);
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time_1 = ca53_get_cycle_count();
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if (fpga) {
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core_timer_delay(CALCULATE_CPU_FREQ_UNIT_US);
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} else {
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timer2_delay(CALCULATE_CPU_FREQ_UNIT_US);
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}
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time_2 = ca53_get_cycle_count();
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if (time_2 > time_1) {
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time_interval = (time_2 - time_1);
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} else {
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temp = 0xFFFFFFFF - time_1;
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time_interval = temp + time_2;
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}
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freq = (time_interval) / (CALCULATE_CPU_FREQ_UNIT_US);
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ca53_cycle_count_stop();
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printf("CHIP[NA51103] =>");
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printf("CPU Freq %d MHz\n", freq);
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return 0;
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}
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#ifdef CONFIG_NVT_FPGA_EMULATION
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U_BOOT_CMD(
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nvt_get_cpu_freq, 2, 1, do_nvt_cpu_get_freq,
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"get cpu freq",
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"[Option] \n"
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" [fpga]\n"
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" [MHz]\n"
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);
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#else
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U_BOOT_CMD(
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nvt_get_cpu_freq, 3, 1, do_nvt_cpu_get_freq,
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"get cpu freq",
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"[MHz]\n"
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);
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#endif
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int do_nvt_cpu_freq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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u32 value = simple_strtoul(argv[1], NULL, 10);
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u32 uiReg;
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if (value > 1400) {
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value = 1400;
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printf("force CPU clk @1400MHz\n");
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}
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switch (argc) {
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case 2:
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switch (value) {
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case 480:
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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if ((uiReg & PLL_CLKSEL_CPUMASK) == PLL_CLKSEL_CPU_480) {
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printf("Already 480MHz(48MHz@FPGA)\n");
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break;
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} else {
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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uiReg &= ~PLL_CLKSEL_CPUMASK;
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uiReg |= PLL_CLKSEL_CPU_480;
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writel(uiReg, (IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS));
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writel(0x34, (IOADDR_CG_REG_BASE + 0xB0));
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while (!(readl(IOADDR_CG_REG_BASE + 0xB0) & (1 << 3)));
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writel(0x28, (IOADDR_CG_REG_BASE + 0xB0));
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printf("Set CPU clk 480MHz(48MHz@FPGA)\n");
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}
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break;
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#ifdef CONFIG_NVT_FPGA_EMULATION
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case 80:
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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if ((uiReg & PLL_CLKSEL_CPUMASK) == PLL_CLKSEL_CPU_80) {
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printf("Already 80MHz(24MHz@FPGA)\n");
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break;
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} else {
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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uiReg &= ~PLL_CLKSEL_CPUMASK;
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uiReg |= PLL_CLKSEL_CPU_80;
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writel(uiReg, (IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS));
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writel(0x34, (IOADDR_CG_REG_BASE + 0xB0));
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while (!(readl(IOADDR_CG_REG_BASE + 0xB0) & (1 << 3)));
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writel(0x28, (IOADDR_CG_REG_BASE + 0xB0));
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printf("Set CPU clk to 80MHz(24MHz@FPGA)\n");
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}
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break;
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case 1000:
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case 1200:
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case 1400:
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default:
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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if ((uiReg & PLL_CLKSEL_CPUMASK) == PLL_CLKSEL_CPU_ARMPLL) {
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printf("Already ARMPLL\n");
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} else {
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uiReg = readl(IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS);
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uiReg &= ~PLL_CLKSEL_CPUMASK;
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uiReg |= PLL_CLKSEL_CPU_ARMPLL;
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writel(uiReg, (IOADDR_CG_REG_BASE + SYSTEM_CLOCK_RATE_OFS));
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writel(0x34, (IOADDR_CG_REG_BASE + 0xB0));
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while (!(readl(IOADDR_CG_REG_BASE + 0xB0) & (1 << 3)));
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writel(0x28, (IOADDR_CG_REG_BASE + 0xB0));
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printf("Set CPU clk APLLMHz\n");
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}
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break;
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#else
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case 1000:
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//CPU 1000 MHz -> CPU-MPLL-125Mhz = 0x14D555
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writel(0x55, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO0_OFS); // B0
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writel(0xD5, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO1_OFS); // B1
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writel(0x14, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO2_OFS); // B2
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printf("Set CPU clk 1000MHz\n");
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break;
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case 1200:
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//CPU 1200 MHz -> CPU-MPLL-150Mhz = 0x190000
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writel(0x00, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO0_OFS); // B0
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writel(0x00, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO1_OFS); // B1
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writel(0x19, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO2_OFS); // B2
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printf("Set CPU clk 1200MHz\n");
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break;
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case 1400:
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//CPU 1400 MHz -> CPU-MPLL-150Mhz = 0x1D2AAA
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writel(0xAA, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO0_OFS); // B0
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writel(0x2A, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO1_OFS); // B1
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writel(0x1D, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO2_OFS); // B2
|
|
printf("Set CPU clk 1200MHz\n");
|
|
break;
|
|
default:
|
|
printf("Not define this CPU Freq %d, use defualt value 1000!\n", value);
|
|
//CPU 1000 MHz -> CPU-MPLL-125Mhz = 0x14D555
|
|
writel(0x55, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO0_OFS); // B0
|
|
writel(0xD5, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO1_OFS); // B1
|
|
writel(0x14, IOADDR_CG_REG_BASE + CPU_CLOCK_RATE_RATIO2_OFS); // B2
|
|
printf("Set CPU clk 1000MHz\n");
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
default:
|
|
printf("CPU:%d => type nvt_cpu_freq <freq>\n", (int)get_cpu_clk());
|
|
return CMD_RET_USAGE;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
U_BOOT_CMD(
|
|
nvt_cpu_freq, 2, 1, do_nvt_cpu_freq,
|
|
"change cpu freq",
|
|
"[MHz]\n"
|
|
#ifdef CONFIG_NVT_FPGA_EMULATION
|
|
"nvt_cpu_freq 480(change to 48MHz@FPGA)\n"
|
|
"nvt_cpu_freq 80(change to 24MHz@FPGA)\n"
|
|
"nvt_cpu_freq !=480 && != 80(will change to ARMPLL@FPGA, check excel)\n"
|
|
#else
|
|
"nvt_cpu_freq 480\n"
|
|
"nvt_cpu_freq 1000\n"
|
|
"nvt_cpu_freq 1200\n"
|
|
"nvt_cpu_freq 1400\n"
|
|
#endif
|
|
);
|
|
|
|
|
|
int do_nvt_ddr_freq(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
|
|
{
|
|
unsigned int freq_ratio;
|
|
unsigned int freq_ratio0, freq_ratio1, freq_ratio2;
|
|
|
|
//0xF0020000 + (0x4000 + 0x400 + 0x20) = 0xF0024400 + 0x20
|
|
freq_ratio0 = readl(IOADDR_CG_REG_BASE + \
|
|
DMA_CLOCK_RATE_RATIO0_OFS);
|
|
|
|
//0xF0020000 + (0x4000 + 0x400 + 0x20) = 0xF0024400 + 0x24
|
|
freq_ratio1 = readl(IOADDR_CG_REG_BASE + \
|
|
DMA_CLOCK_RATE_RATIO1_OFS);
|
|
|
|
//0xF0020000 + (0x4000 + 0x400 + 0x20) = 0xF0024400 + 0x28
|
|
freq_ratio2 = readl(IOADDR_CG_REG_BASE + \
|
|
DMA_CLOCK_RATE_RATIO2_OFS);
|
|
freq_ratio = freq_ratio0 | (freq_ratio1 << 8) | \
|
|
(freq_ratio2 << 16);
|
|
|
|
freq_ratio = (freq_ratio << 3);
|
|
printf("DMA clock rate = %d => [%d]MHz\r\n", (12 * freq_ratio / 131072), ((12 * freq_ratio / 131072) >> 1));
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(
|
|
nvt_get_ddr_freq, 2, 1, do_nvt_ddr_freq,
|
|
"get ddr freq/type\n",
|
|
"\n"
|
|
);
|