420 lines
11 KiB
C
Executable File
420 lines
11 KiB
C
Executable File
/*
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Base IO address for NT98321
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Base IO address for NT98321.
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@file IOAddress.h
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@ingroup
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2016. All rights reserved.
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*/
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#ifndef _IOADDRESS_H
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#define _IOADDRESS_H
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/*
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@addtogroup
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*/
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//@{
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#define IOADDR_GLOBAL_BASE (0xF0000000)
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// ---------------------------------------------
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// System category 0
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// ---------------------------------------------
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// SDRAM Controller
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#define IOADDR_DRAM_REG_BASE (IOADDR_GLOBAL_BASE+0x0A000000)
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// Top
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#define IOADDR_TOP_REG_BASE (IOADDR_GLOBAL_BASE+0x0E030000)
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// CG
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#define IOADDR_CG_REG_BASE (IOADDR_GLOBAL_BASE+0x0E000000)
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// PAD
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#define IOADDR_PAD_REG_BASE (IOADDR_GLOBAL_BASE+0x0E040000)
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// Timer
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#define IOADDR_TIMER_REG_BASE (IOADDR_GLOBAL_BASE+0x0E8C0000)
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// WDT (Watch Dog Timer)
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#define IOADDR_WDT_REG_BASE (IOADDR_GLOBAL_BASE+0x0E8A0000)
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// RTC & Power Button
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#define IOADDR_RTC_REG_BASE (IOADDR_GLOBAL_BASE+0x0E880000)
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// GPIO
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#define IOADDR_GPIO_REG_BASE (IOADDR_GLOBAL_BASE+0x0E400000)
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// Interrupt
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// **** Note ****
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// Must check INT_CTRL_ADDR in \Common\Common_src\Kernel\IntHnder.s
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#define IOADDR_INTERRUPT_REG_BASE (IOADDR_GLOBAL_BASE+0x00080000)
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// GIC Interrupt
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#define IOADDR_GIC_REG_BASE (IOADDR_GLOBAL_BASE+0x01500000)
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// CC
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#define IOADDR_CC_REG_BASE (IOADDR_GLOBAL_BASE+0x00090000)
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// PMC
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#define IOADDR_PMC_REG_BASE (IOADDR_GLOBAL_BASE+0x000A0000)
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// ---------------------------------------------
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// System category 1
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// ---------------------------------------------
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// SDRAM Controller 2
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#define IOADDR_DRAM2_REG_BASE (IOADDR_GLOBAL_BASE+0x00100000)
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// DRTC
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#define IOADDR_DRTC_REG_BASE (IOADDR_GLOBAL_BASE+0x00110000)
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// ---------------------------------------------
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// IO category 0
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// ---------------------------------------------
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// BMC
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#define IOADDR_BMC_REG_BASE (IOADDR_GLOBAL_BASE+0x00200000)
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// PWM
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#define IOADDR_PWM_REG_BASE (IOADDR_GLOBAL_BASE+0x00210000)
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// I2C
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#define IOADDR_I2C_REG_BASE (IOADDR_GLOBAL_BASE+0x00220000)
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// SPI
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#define IOADDR_SPI_REG_BASE (IOADDR_GLOBAL_BASE+0x00230000)
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// SIF
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#define IOADDR_SIF_REG_BASE (IOADDR_GLOBAL_BASE+0x00240000)
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// Remote
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#define IOADDR_REMOTE_REG_BASE (IOADDR_GLOBAL_BASE+0x00250000)
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// ADC
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#define IOADDR_ADC_REG_BASE (IOADDR_GLOBAL_BASE+0x00260000)
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// LVDS / HiSPi
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#define IOADDR_LVDS_REG_BASE (IOADDR_GLOBAL_BASE+0x00270000)
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// MIPI - CSI
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#define IOADDR_CSI_REG_BASE (IOADDR_GLOBAL_BASE+0x00280000)
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// UART
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#define IOADDR_UART_REG_BASE (IOADDR_GLOBAL_BASE+0x00290000)
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// Vx1
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#define IOADDR_VX1_REG_BASE (IOADDR_GLOBAL_BASE+0x002A0000)
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// Ethernet
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#define IOADDR_ETH_REG_BASE (IOADDR_GLOBAL_BASE+0x002B0000)
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// SLVS-EC
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#define IOADDR_SLVSEC_REG_BASE (IOADDR_GLOBAL_BASE+0x002C0000)
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// CAN-BUS
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#define IOADDR_CANBUS_REG_BASE (IOADDR_GLOBAL_BASE+0x002D0000)
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// ---------------------------------------------
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// IO category 1
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// ---------------------------------------------
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// UART2
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#define IOADDR_UART2_REG_BASE (IOADDR_GLOBAL_BASE+0x00300000)
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// UART3
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#define IOADDR_UART3_REG_BASE (IOADDR_GLOBAL_BASE+0x00310000)
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// SPI2
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#define IOADDR_SPI2_REG_BASE (IOADDR_GLOBAL_BASE+0x00320000)
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// MIPI - CSI2
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#define IOADDR_CSI2_REG_BASE (IOADDR_GLOBAL_BASE+0x00330000)
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// SPI3
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#define IOADDR_SPI3_REG_BASE (IOADDR_GLOBAL_BASE+0x00340000)
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// I2C2
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#define IOADDR_I2C2_REG_BASE (IOADDR_GLOBAL_BASE+0x00350000)
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// SPI4
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#define IOADDR_SPI4_REG_BASE (IOADDR_GLOBAL_BASE+0x00360000)
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// LVDS2
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#define IOADDR_LVDS2_REG_BASE (IOADDR_GLOBAL_BASE+0x00370000)
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// UART4
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#define IOADDR_UART4_REG_BASE (IOADDR_GLOBAL_BASE+0x00380000)
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// SPI5
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#define IOADDR_SPI5_REG_BASE (IOADDR_GLOBAL_BASE+0x00390000)
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// I2C3
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#define IOADDR_I2C3_REG_BASE (IOADDR_GLOBAL_BASE+0x003A0000)
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// I2C4
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#define IOADDR_I2C4_REG_BASE (IOADDR_GLOBAL_BASE+0x003B0000)
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// I2C5
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#define IOADDR_I2C5_REG_BASE (IOADDR_GLOBAL_BASE+0x003C0000)
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// I2C6
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#define IOADDR_I2C6_REG_BASE (IOADDR_GLOBAL_BASE+0x003D0000)
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// I2C7
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#define IOADDR_I2C7_REG_BASE (IOADDR_GLOBAL_BASE+0x003E0000)
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// Vx1_2
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#define IOADDR_VX12_REG_BASE (IOADDR_GLOBAL_BASE+0x003F0000)
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// ---------------------------------------------
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// IO category 2
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// ---------------------------------------------
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// LVDS3
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#define IOADDR_LVDS3_REG_BASE (IOADDR_GLOBAL_BASE+0x00E00000)
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// LVDS4
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#define IOADDR_LVDS4_REG_BASE (IOADDR_GLOBAL_BASE+0x00E10000)
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// LVDS5
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#define IOADDR_LVDS5_REG_BASE (IOADDR_GLOBAL_BASE+0x00E20000)
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// LVDS6
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#define IOADDR_LVDS6_REG_BASE (IOADDR_GLOBAL_BASE+0x00E30000)
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// LVDS7
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#define IOADDR_LVDS7_REG_BASE (IOADDR_GLOBAL_BASE+0x00E40000)
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// LVDS8
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#define IOADDR_LVDS8_REG_BASE (IOADDR_GLOBAL_BASE+0x00E50000)
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// MIPI - CSI3
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#define IOADDR_CSI3_REG_BASE (IOADDR_GLOBAL_BASE+0x00E60000)
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// MIPI - CSI4
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#define IOADDR_CSI4_REG_BASE (IOADDR_GLOBAL_BASE+0x00E70000)
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// MIPI - CSI5
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#define IOADDR_CSI5_REG_BASE (IOADDR_GLOBAL_BASE+0x00E80000)
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// MIPI - CSI6
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#define IOADDR_CSI6_REG_BASE (IOADDR_GLOBAL_BASE+0x00E90000)
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// MIPI - CSI7
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#define IOADDR_CSI7_REG_BASE (IOADDR_GLOBAL_BASE+0x00EA0000)
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// MIPI - CSI8
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#define IOADDR_CSI8_REG_BASE (IOADDR_GLOBAL_BASE+0x00EB0000)
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// ---------------------------------------------
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// Storage category 0
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// ---------------------------------------------
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// NAND
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#define IOADDR_NAND_REG_BASE (IOADDR_GLOBAL_BASE+0x0A900000)
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// SDIO
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#define IOADDR_SDIO_REG_BASE (IOADDR_GLOBAL_BASE+0x00420000)
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// ---------------------------------------------
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// Storage category 1
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// ---------------------------------------------
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// SDIO2
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#define IOADDR_SDIO2_REG_BASE (IOADDR_GLOBAL_BASE+0x00500000)
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// SDIO3
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#define IOADDR_SDIO3_REG_BASE (IOADDR_GLOBAL_BASE+0x00510000)
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// ---------------------------------------------
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// Misc category 0
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// ---------------------------------------------
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// USB
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#define IOADDR_USB_REG_BASE (IOADDR_GLOBAL_BASE+0x00600000)
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// USB3
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#define IOADDR_USB3_REG_BASE (IOADDR_GLOBAL_BASE+0x01700000)
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// Crypto
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#define IOADDR_CRYPTO_REG_BASE (IOADDR_GLOBAL_BASE+0x00620000)
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// DAI
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#define IOADDR_DAI_REG_BASE (IOADDR_GLOBAL_BASE+0x00630000)
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// EAC
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#define IOADDR_EAC_REG_BASE (IOADDR_GLOBAL_BASE+0x00640000)
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// TSMux
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#define IOADDR_TSMUX_REG_BASE (IOADDR_GLOBAL_BASE+0x00650000)
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// eFUSE
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#define IOADDR_EFUSE_REG_BASE (IOADDR_GLOBAL_BASE+0x00660000)
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// USB3-CTRL
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#define IOADDR_USB3CTL_REG_BASE (IOADDR_GLOBAL_BASE+0x00670000)
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// TSDEMux
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#define IOADDR_TSDEMUX_REG_BASE (IOADDR_GLOBAL_BASE+0x00680000)
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// ---------------------------------------------
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// Misc category 1
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// ---------------------------------------------
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// ---------------------------------------------
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// Display category 0
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// ---------------------------------------------
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// IDE
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#define IOADDR_IDE_REG_BASE (IOADDR_GLOBAL_BASE+0x00800000)
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// MI
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#define IOADDR_MI_REG_BASE (IOADDR_GLOBAL_BASE+0x00810000)
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// HDMI
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#define IOADDR_HDMI_REG_BASE (IOADDR_GLOBAL_BASE+0x00820000)
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// TV
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#define IOADDR_TV_REG_BASE (IOADDR_GLOBAL_BASE+0x00830000)
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// MIPI-DSI
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#define IOADDR_DSI_REG_BASE (IOADDR_GLOBAL_BASE+0x00840000)
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// ---------------------------------------------
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// Display category 1
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// ---------------------------------------------
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// IDE2
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#define IOADDR_IDE2_REG_BASE (IOADDR_GLOBAL_BASE+0x00900000)
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// ---------------------------------------------
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// Codec category 0
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// ---------------------------------------------
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// JPEG
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#define IOADDR_JPEG_REG_BASE (IOADDR_GLOBAL_BASE+0x00A00000)
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// H264
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#define IOADDR_H264_REG_BASE (IOADDR_GLOBAL_BASE+0x00A10000)
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// ---------------------------------------------
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// Codec category 1
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// ---------------------------------------------
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// ---------------------------------------------
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// IPP category 0
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// ---------------------------------------------
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// SIE
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#define IOADDR_SIE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C00000)
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// COPY
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#define IOADDR_COPY_REG_BASE (IOADDR_GLOBAL_BASE+0x00C10000)
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// DCE
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#define IOADDR_DCE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C20000)
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// IPE
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#define IOADDR_IPE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C30000)
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// IME
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#define IOADDR_IME_REG_BASE (IOADDR_GLOBAL_BASE+0x00C40000)
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// DIS
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#define IOADDR_DIS_REG_BASE (IOADDR_GLOBAL_BASE+0x00C50000)
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// FDE
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#define IOADDR_FDE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C60000)
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// IFE
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#define IOADDR_IFE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C70000)
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// Graphic
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#define IOADDR_GRAPHIC_REG_BASE (IOADDR_GLOBAL_BASE+0x00C80000)
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// ISE
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#define IOADDR_ISE_REG_BASE (IOADDR_GLOBAL_BASE+0x00C90000)
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// Affine
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#define IOADDR_AFFINE_REG_BASE (IOADDR_GLOBAL_BASE+0x00CA0000)
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// CNN
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#define IOADDR_CNN_REG_BASE (IOADDR_GLOBAL_BASE+0x00CB0000)
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// TGE
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#define IOADDR_TGE_REG_BASE (IOADDR_GLOBAL_BASE+0x00CC0000)
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// DRE
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#define IOADDR_DRE_REG_BASE (IOADDR_GLOBAL_BASE+0x00CD0000)
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// RHE
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#define IOADDR_RHE_REG_BASE (IOADDR_GLOBAL_BASE+0x00CE0000)
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// Rotation
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#define IOADDR_ROT_REG_BASE (IOADDR_GLOBAL_BASE+0x00CF0000)
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// ---------------------------------------------
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// IPP category 1
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// ---------------------------------------------
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// IFE2
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#define IOADDR_IFE2_REG_BASE (IOADDR_GLOBAL_BASE+0x00D00000)
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// Graphic2
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#define IOADDR_GRAPHIC2_REG_BASE (IOADDR_GLOBAL_BASE+0x00D10000)
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// SIE2
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#define IOADDR_SIE2_REG_BASE (IOADDR_GLOBAL_BASE+0x00D20000)
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// SIE3
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#define IOADDR_SIE3_REG_BASE (IOADDR_GLOBAL_BASE+0x00D30000)
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// SIE4
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#define IOADDR_SIE4_REG_BASE (IOADDR_GLOBAL_BASE+0x00D40000)
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// SIE5
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#define IOADDR_SIE5_REG_BASE (IOADDR_GLOBAL_BASE+0x00D50000)
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// SIE6
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#define IOADDR_SIE6_REG_BASE (IOADDR_GLOBAL_BASE+0x00D60000)
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// SIE7
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#define IOADDR_SIE7_REG_BASE (IOADDR_GLOBAL_BASE+0x00D70000)
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// SIE8
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#define IOADDR_SIE8_REG_BASE (IOADDR_GLOBAL_BASE+0x00D80000)
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// IVE
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#define IOADDR_IVE_REG_BASE (IOADDR_GLOBAL_BASE+0x00D90000)
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// SVM
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#define IOADDR_SVM_REG_BASE (IOADDR_GLOBAL_BASE+0x00DA0000)
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// SDE
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#define IOADDR_SDE_REG_BASE (IOADDR_GLOBAL_BASE+0x00DB0000)
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// ---------------------------------------------
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// DSP category 0
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// ---------------------------------------------
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// DSP
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#define IOADDR_DSP_REG_BASE (IOADDR_GLOBAL_BASE+0x01430000)
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// DSP2
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#define IOADDR_DSP2_REG_BASE (IOADDR_GLOBAL_BASE+0x01440000)
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//@}
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// RDE - Obselete
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#define IOADDR_RDE_REG_BASE (IOADDR_GLOBAL_BASE+0x00FFFFFF)
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#endif
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