159 lines
6.3 KiB
C
Executable File
159 lines
6.3 KiB
C
Executable File
/*
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Register definition header file for CG module of NA51055.
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This file is the header file that define the address offset
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definition of registers of CG module.
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@file cg-reg.h
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Copyright Novatek Microelectronics Corp. 2018. All rights reserved
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _CG_REG_H
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#define _CG_REG_H
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#include "hardware.h"
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/* PLL */
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#define CG_PLL_EN_REG_OFFSET 0x00
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#define CG_PLL_STAT_REG_OFFSET 0x04
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/* Clock source control */
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#define CG_SYS_CLK_RATE_REG_OFFSET 0x10
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#define CG_IPP_CLK_RATE_REG0_OFFSET 0x14
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#define CG_IPP_CLK_RATE_REG1_OFFSET 0x18
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#define CG_CODEC_CLK_RATE_REG_OFFSET 0x1C
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#define CG_PERI_CLK_RATE_REG0_OFFSET 0x20
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#define CG_PERI_CLK_RATE_REG1_OFFSET 0x24
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#define CG_PERI_CLK_RATE_REG2_OFFSET 0x28
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#define CG_PERI_CLK_RATE_REG3_OFFSET 0x2C
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/* Clock rate control */
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#define CG_IPP_CLK_DIV_REG0_OFFSET 0x30
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#define CG_VIDEO_CLK_DIV_REG_OFFSET 0x34
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#define CG_PERI_CLK_DIV_REG0_OFFSET 0x38
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#define CG_SDIO_CLK_DIV_REG_OFFSET 0x3C
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#define CG_PERI_CLK_DIV_REG1_OFFSET 0x40
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#define CG_SPI_CLK_DIV_REG0_OFFSET 0x44
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#define CG_SPI_CLK_DIV_REG1_OFFSET 0x48
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#define CG_SPI_CLK_DIV_REG2_OFFSET 0x64
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#define CG_UART_CLK_DIV_REG0_OFFSET 0x4C
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/* PWM clock rate control */
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#define CG_PWM_CLK_RATE_REG0_OFFSET 0x50
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#define CG_PWM_CLK_RATE_REG1_OFFSET 0x54
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#define CG_PWM_CLK_RATE_REG2_OFFSET 0x58
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#define CG_PERI_CLK_DIV_REG2_OFFSET 0x60
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/* Clock enable/disable control */
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#define CG_CLK_EN_REG0_OFFSET 0x70
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#define CG_CLK_EN_REG1_OFFSET 0x74
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#define CG_CLK_EN_REG2_OFFSET 0x78
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#define CG_CLK_EN_REG3_OFFSET 0x7C
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/* Module reset control */
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#define CG_SYS_RESET_REG0_OFFSET 0x80
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#define CG_SYS_RESET_REG1_OFFSET 0x84
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#define CG_SYS_RESET_REG2_OFFSET 0x88
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/* Low power control */
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#define CG_SLEEP_MODE_REG_OFFSET 0xA0
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#define CG_CLK_AUTO_GATING_REG0_OFFSET 0xB0
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#define CG_CLK_AUTO_GATING_REG1_OFFSET 0xB4
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#define CG_APB_CLK_AUTO_GATING_REG0_OFFSET 0xC0
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#define CG_APB_CLK_AUTO_GATING_REG1_OFFSET 0xC4
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#define CG_APB_CLK_AUTO_GATING_REG2_OFFSET 0xC8
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#define CG_PLL_MCU_FLAG_REG_OFFSET 0x1180
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/* PLL clock rate control */
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#define CG_PLL8_CLK_RATE0_REG_OFFSET (0x4400 + 0x20)
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#define CG_PLL8_CLK_RATE1_REG_OFFSET (0x4400 + 0x24)
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#define CG_PLL8_CLK_RATE2_REG_OFFSET (0x4400 + 0x2C)
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/* 520 sdio spread spectrum */
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#define CG_PLL4_SPREAD_SPECTRUM_REG0_OFFSET 0x11C8
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#define CG_PLL4_SPREAD_SPECTRUM_REG1_OFFSET 0x11CC
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#define CG_PLL4_SPREAD_SPECTRUM_REG2_OFFSET 0x11D0
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#define CG_PLL4_SPREAD_SPECTRUM_REG3_OFFSET 0x11D4
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#define CG_PLL3_CLK_RATE0_REG_OFFSET (0x4480 + 0x20)
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#define CG_PLL3_CLK_RATE1_REG_OFFSET (0x4480 + 0x24)
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#define CG_PLL3_CLK_RATE2_REG_OFFSET (0x4480 + 0x2C)
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#define CG_PLL14_CLK_RATE0_REG_OFFSET 0x1228
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#define CG_PLL14_CLK_RATE1_REG_OFFSET 0x122C
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#define CG_PLL14_CLK_RATE2_REG_OFFSET 0x1230
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#define CG_PLL11_CLK_RATE0_REG_OFFSET (0x4440 + 0x20)
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#define CG_PLL11_CLK_RATE1_REG_OFFSET (0x4440 + 0x24)
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#define CG_PLL11_CLK_RATE2_REG_OFFSET (0x4440 + 0x2C)
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#define CG_PLL6_CLK_RATE0_REG_OFFSET (0x44C0 + 0x20)
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#define CG_PLL6_CLK_RATE1_REG_OFFSET (0x44C0 + 0x24)
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#define CG_PLL6_CLK_RATE2_REG_OFFSET (0x44C0 + 0x2C)
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#define CG_PLL10_CLK_RATE0_REG_OFFSET 0x12A8
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#define CG_PLL10_CLK_RATE1_REG_OFFSET 0x12AC
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#define CG_PLL10_CLK_RATE2_REG_OFFSET 0x12B0
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#define CG_PLLF320_CLK_RATE0_REG_OFFSET 0x12C8
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#define CG_PLLF320_CLK_RATE1_REG_OFFSET 0x12CC
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#define CG_PLLF320_CLK_RATE2_REG_OFFSET 0x12D0
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#define CG_PLL7_CLK_RATE0_REG_OFFSET (0x45C0 + 0x20)
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#define CG_PLL7_CLK_RATE1_REG_OFFSET (0x45C0 + 0x24)
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#define CG_PLL7_CLK_RATE2_REG_OFFSET (0x45C0 + 0x2C)
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#define CG_PLL13_CLK_RATE0_REG_OFFSET 0x1304
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#define CG_PLL13_CLK_RATE1_REG_OFFSET 0x1308
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#define CG_PLL13_CLK_RATE2_REG_OFFSET 0x130C
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#define CG_PLL4_CLK_RATE0_REG_OFFSET 0x1318
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#define CG_PLL4_CLK_RATE1_REG_OFFSET 0x131C
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#define CG_PLL4_CLK_RATE2_REG_OFFSET 0x1320
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#define CG_PLL12_CLK_RATE0_REG_OFFSET (0x4580 + 0x20)
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#define CG_PLL12_CLK_RATE1_REG_OFFSET (0x4580 + 0x24)
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#define CG_PLL12_CLK_RATE2_REG_OFFSET (0x4580 + 0x2C)
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#define CG_PLL9_CLK_RATE0_REG_OFFSET (0x4500 + 0x20)
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#define CG_PLL9_CLK_RATE1_REG_OFFSET (0x4500 + 0x24)
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#define CG_PLL9_CLK_RATE2_REG_OFFSET (0x4500 + 0x2C)
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#define CG_PLL5_CLK_RATE0_REG_OFFSET (0x4540 + 0x20)
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#define CG_PLL5_CLK_RATE1_REG_OFFSET (0x4540 + 0x24)
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#define CG_PLL5_CLK_RATE2_REG_OFFSET (0x4540 + 0x2C)
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#define CG_PLL15_CLK_RATE0_REG_OFFSET 0x13DC
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#define CG_PLL15_CLK_RATE1_REG_OFFSET 0x13E0
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#define CG_PLL15_CLK_RATE2_REG_OFFSET 0x13E4
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/* 560 sdio spread spectrum */
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#define CG_PLL9_SPREAD_SPECTRUM_REG0_OFFSET (0x4500 + 0x0C)
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#define CG_PLL9_SPREAD_SPECTRUM_REG1_OFFSET (0x4500 + 0x1C)
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#define CG_PLL9_SPREAD_SPECTRUM_REG2_OFFSET (0x4500 + 0x10)
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#define CG_PLL9_SPREAD_SPECTRUM_REG3_OFFSET (0x4500 + 0x14)
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#define CG528_ARMPLL_CONTROL0_REG_OFFSET (0x4340)
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#define CG528_ARMPLL_CONTROL1_REG_OFFSET (0x4344)
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#define CG528_ARMPLL_CONTROL2_REG_OFFSET (0x43C8)
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/* 528 sdio spread spectrum */
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#define CG528_PLL4_SPREAD_SPECTRUM_REG0_OFFSET (0x44C0+0x0C)
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#define CG528_PLL4_SPREAD_SPECTRUM_REG1_OFFSET (0x44C0+0x1C)
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#define CG528_PLL4_SPREAD_SPECTRUM_REG2_OFFSET (0x44C0+0x10)
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#define CG528_PLL4_SPREAD_SPECTRUM_REG3_OFFSET (0x44C0+0x14)
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#define CG528_PLL3_CLK_RATE0_REG_OFFSET (0x4400+0x20)
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#define CG528_PLL4_CLK_RATE0_REG_OFFSET (0x44C0+0x20)
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#define CG528_PLL5_CLK_RATE0_REG_OFFSET (0x4600+0x20)
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#define CG528_PLL6_CLK_RATE0_REG_OFFSET (0x4500+0x20)
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#define CG528_PLL7_CLK_RATE0_REG_OFFSET (0x46C0+0x20)
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#define CG528_PLL8_CLK_RATE0_REG_OFFSET (0x47C0+0x20)
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#define CG528_PLL9_CLK_RATE0_REG_OFFSET (0x4540+0x20)
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#define CG528_PLL10_CLK_RATE0_REG_OFFSET (0x4480+0x20)
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#define CG528_PLL11_CLK_RATE0_REG_OFFSET (0x4780+0x20)
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#define CG528_PLL12_CLK_RATE0_REG_OFFSET (0x4640+0x20)
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#define CG528_PLL13_CLK_RATE0_REG_OFFSET (0x4800+0x20)
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#define CG528_PLL14_CLK_RATE0_REG_OFFSET (0x4440+0x20)
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#define CG528_PLL15_CLK_RATE0_REG_OFFSET (0x4740+0x20)
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#define CG528_PLL16_CLK_RATE0_REG_OFFSET (0x4580+0x20)
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#define CG528_PLL17_CLK_RATE0_REG_OFFSET (0x4700+0x20)
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#define CG528_PLL18_CLK_RATE0_REG_OFFSET (0x4680+0x20)
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#define CG528_PLLF320_CLK_RATE0_REG_OFFSET (0x45C0+0x20)
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#endif
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