211 lines
6.2 KiB
C
Executable File
211 lines
6.2 KiB
C
Executable File
/*
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Register offset and bit definition for ADC module
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Register offset and bit definition for ADC module.
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@file adc_reg.h
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2018. All rights reserved
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _ADC_REG_H
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#define _ADC_REG_H
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#include <mach/nvt-io.h>
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#include <linux/clk.h>
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#define ADC_CTRL_REG_OFS 0x00
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union ADC_CTRL_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_mode:1; // ADC channel 0 mode
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unsigned int ain1_mode:1; // ADC channel 1 mode
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unsigned int ain2_mode:1; // ADC channel 2 mode
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unsigned int ain3_mode:1; // ADC channel 3 mode
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unsigned int reserved0:8; // Reserved
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unsigned int clkdiv:5; // ADC clock pre-scalar
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unsigned int reserved1:3; // Reserved
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unsigned int sampavg:2; // ADC sample to average
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unsigned int reserved2:1; // Reserved
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unsigned int adc_en:1; // ADC converter enable bit
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unsigned int extsamp_cnt:4; // Extra ADC sample clock count
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unsigned int reserved3:4;
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} bit;
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};
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//0x04 ADC one-shot Register
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#define ADC_ONESHOT_REG_OFS 0x04
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union ADC_ONESHOT_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_oneshot:1; // ADC channel 0 one-shot start
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unsigned int ain1_oneshot:1; // ADC channel 1 one-shot start
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unsigned int ain2_oneshot:1; // ADC channel 2 one-shot start
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unsigned int ain3_oneshot:1; // ADC channel 3 one-shot start
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unsigned int reserved0:28;
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} bit;
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};
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//0x08 ADC interrupt control Register
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#define ADC_INTCTRL_REG_OFS 0x08
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union ADC_INTCTRL_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_inten:1; // ADC channel 0 data ready interrupt enable
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unsigned int ain1_inten:1; // ADC channel 1 data ready interrupt enable
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unsigned int ain2_inten:1; // ADC channel 2 data ready interrupt enable
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unsigned int ain3_inten:1; // ADC channel 3 data ready interrupt enable
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unsigned int aintr0_inten:1;
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unsigned int aintr1_inten:1;
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unsigned int aintr2_inten:1;
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unsigned int reserved0:25;
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} bit;
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};
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//0x0C ADC status Register
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#define ADC_STATUS_REG_OFS 0x0C
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union ADC_STATUS_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_datardy:1; // ADC channel 0 data ready status
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unsigned int ain1_datardy:1; // ADC channel 1 data ready status
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unsigned int ain2_datardy:1; // ADC channel 2 data ready status
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unsigned int ain3_datardy:1; // ADC channel 3 data ready status
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unsigned int aintr0:1;
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unsigned int aintr1:1;
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unsigned int aintr2:1;
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unsigned int reserved2:25;
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} bit;
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};
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//0x10 ADC value trigger Register
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#define ADC_TRIGCTRL_REG_OFS 0x10
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union ADC_TRIGCTRL_REG {
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uint32_t reg;
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struct {
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unsigned int trig0_en:1; // ADC channel 0 value trigger enable
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unsigned int trig1_en:1; // ADC channel 1 value trigger enable
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unsigned int trig2_en:1; // ADC channel 2 value trigger enable
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unsigned int reserved0:1;
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unsigned int trig0_range:1; // ADC channel 0 value trigger range
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unsigned int trig1_range:1; // ADC channel 1 value trigger range
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unsigned int trig2_range:1; // ADC channel 2 value trigger range
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unsigned int reserved1:1;
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unsigned int trig0_mode:1; // ADC channel 0 value trigger mode
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unsigned int trig1_mode:1; // ADC channel 1 value trigger mode
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unsigned int trig2_mode:1; // ADC channel 2 value trigger mode
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unsigned int reserved2:5;
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unsigned int trig0_id:2; // ADC channel trigger0 ID
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unsigned int reserved3:2;
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unsigned int trig1_id:2; // ADC channel trigger1 ID
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unsigned int reserved4:2;
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unsigned int trig2_id:2; // ADC channel trigger2 ID
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unsigned int reserved5:6;
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} bit;
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};
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//0x14 ADC value range Register 0
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#define ADC_TRIGVAL0_REG_OFS 0x14
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union ADC_TRIGVAL0_REG {
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uint32_t reg;
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struct {
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unsigned int trig0_start:8; // ADC channel 0 trigger value START
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unsigned int trig0_end:8; // ADC channel 0 trigger value END
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unsigned int reserved0:16;
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} bit;
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};
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//0x18 ADC value range Register 1
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#define ADC_TRIGVAL1_REG_OFS 0x18
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union ADC_TRIGVAL1_REG {
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uint32_t reg;
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struct {
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unsigned int trig1_start:8; // ADC channel 1 trigger value START
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unsigned int trig1_end:8; // ADC channel 1 trigger value END
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unsigned int reserved0:16;
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} bit;
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};
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//0x1C ADC value range Register 2
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#define ADC_TRIGVAL2_REG_OFS 0x1C
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union ADC_TRIGVAL2_REG {
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uint32_t reg;
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struct {
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unsigned int trig2_start:8; // ADC channel 2 trigger value START
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unsigned int trig2_end:8; // ADC channel 2 trigger value END
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unsigned int reserved0:16;
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} bit;
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};
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//0x20 ADC divide Register 0
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#define ADC_DIV0_REG_OFS 0x20
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union ADC_DIV0_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_div:8; // ADC channel 0 divider
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unsigned int ain1_div:8; // ADC channel 1 divider
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unsigned int ain2_div:8; // ADC channel 2 divider
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unsigned int ain3_div:8; // ADC channel 3 divider
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} bit;
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};
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//0x30 ADC channel 0 data Register
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#define ADC_AIN0_DATA_REG_OFS 0x30
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union ADC_AIN0_DATA_REG {
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uint32_t reg;
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struct {
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unsigned int ain0_data:9; // ADC channel 0 data
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unsigned int reserved0:23;
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} bit;
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};
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//0x34 ADC channel 1 data Register
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#define ADC_AIN1_DATA_REG_OFS 0x34
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union ADC_AIN1_DATA_REG {
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uint32_t reg;
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struct {
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unsigned int ain1_data:9; // ADC channel 1 data
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unsigned int reserved0:23;
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} bit;
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};
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//0x38 ADC channel 2 data Register
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#define ADC_AIN2_DATA_REG_OFS 0x38
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union ADC_AIN2_DATA_REG {
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uint32_t reg;
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struct {
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unsigned int ain2_data:9; // ADC channel 2 data
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unsigned int reserved0:23;
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} bit;
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};
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//0x3C ADC channel 3 data Register
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#define ADC_AIN3_DATA_REG_OFS 0x3C
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union ADC_AIN3_DATA_REG {
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uint32_t reg;
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struct {
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unsigned int ain3_data:9; // ADC channel 3 data
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unsigned int reserved0:23;
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} bit;
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};
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//0x40 Thermal sensor configure Register
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#define THERMAL_SENSOR_CONFIGURE_REG_OFS 0x40
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union THERMAL_SENSOR_CONFIGURE_REG {
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uint32_t reg;
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struct {
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unsigned int ain_avg_cnt:3; // average count
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unsigned int reserved0:1;
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unsigned int ain_avg_id:2; // average channel id
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unsigned int reserved1:10;
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unsigned int ain_avg_out:9; // average value
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unsigned int reserved2:7;
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} bit;
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};
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#endif
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