86 lines
3.3 KiB
C
Executable File
86 lines
3.3 KiB
C
Executable File
/*
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Register definition header file for CG module of NA51055.
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This file is the header file that define the address offset
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definition of registers of CG module.
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@file cg-reg.h
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Copyright Novatek Microelectronics Corp. 2018. All rights reserved
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#ifndef _CG_REG_H
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#define _CG_REG_H
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#include "hardware.h"
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/* PLL */
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#define CG_PLL_EN_REG_OFFSET 0x00
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#define CG_PLL_STAT_REG_OFFSET 0x04
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/* Module reset control */
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#define CG_CPU_DSP_RESET_REG_OFFSET 0x4C
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#define CG_MODULE_RESET_REG0_OFFSET 0x50
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#define CG_MODULE_RESET_REG1_OFFSET 0x54
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/* APB reset control */
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#define CG_APB_RESET_REG0_OFFSET 0x58
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#define CG_APB_RESET_REG1_OFFSET 0x5C
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/* Bus clock enable/disable control */
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#define CG_BUS_CLK_GATING_REG0_OFFSET 0x60
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#define CG_BUS_CLK_GATING_REG1_OFFSET 0x64
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#define CG_BUS_CLK_GATING_REG2_OFFSET 0x68
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#define CG_BUS_CLK_GATING_REG3_OFFSET 0x6C
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/* APB clock enable/disable control */
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#define CG_APB_CLK_GATING_REG0_OFFSET 0x70
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#define CG_APB_CLK_GATING_REG1_OFFSET 0x74
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#define CG_APB_CLK_GATING_REG2_OFFSET 0x78
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/* MAC Cofiguration */
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#define CG_MAC_CONFIG_REG_OFFSET 0xE4
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/* Clock source and rate control */
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#define CG_CPU_CKCTRL_REG_OFFSET 0x100
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#define CG_H264D_CKCTRL_REG_OFFSET 0x158
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#define CG_OSG_CKCTRL_REG_OFFSET 0x15C
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#define CG_SSCA_CKCTRL_REG_OFFSET 0x160
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#define CG_CRYPTO_CKCTRL_REG_OFFSET 0x164
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#define CG_H265D_CKCTRL_REG_OFFSET 0x168
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#define CG_VPE536_CKCTRL_REG_OFFSET 0x16C
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#define CG_EXT_CKCTRL_REG_OFFSET 0x170
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#define CG_LCD_CKCTRL_REG_OFFSET 0x174
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#define CG_ETH_CKCTRL_REG_OFFSET 0x178
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#define CG_VENC_CKCTRL_REG_OFFSET 0x17C
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#define CG_HDMI_SPI_CKCTRL_REG_OFFSET 0x180
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#define CG_SSP_CKCTRL_REG0_OFFSET 0x184
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#define CG_SSP_CKCTRL_REG1_OFFSET 0x188
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#define CG_SDC_UART_SSP_CKCTRL_REG_OFFSET 0x18C
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#define CG_VCAP_CKCTRL_REG_OFFSET 0x190
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#define CG_VPE316_CKCTRL_REG_OFFSET 0x194
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/* PLL clock rate control */
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#define CG_PLL0_CLK_RATE0_REG_OFFSET 0x10400
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#define CG_PLL1_CLK_RATE0_REG_OFFSET 0x10440
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#define CG_PLL2_CLK_RATE0_REG_OFFSET 0x10480
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#define CG_PLL3_CLK_RATE0_REG_OFFSET 0x104C0
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#define CG_PLL4_CLK_RATE0_REG_OFFSET 0x10500
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#define CG_PLL5_CLK_RATE0_REG_OFFSET 0x10800
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#define CG_PLL6_CLK_RATE0_REG_OFFSET 0x10540
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#define CG_PLL7_CLK_RATE0_REG_OFFSET 0x10580
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#define CG_PLL8_CLK_RATE0_REG_OFFSET 0x105C0
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#define CG_PLL9_CLK_RATE0_REG_OFFSET 0x10600
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#define CG_PLL10_CLK_RATE0_REG_OFFSET 0x10640
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#define CG_PLL11_CLK_RATE0_REG_OFFSET 0x10680
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#define CG_PLL12_CLK_RATE0_REG_OFFSET 0x106C0
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#define CG_PLL13_CLK_RATE0_REG_OFFSET 0x10700
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#define CG_PLL14_CLK_RATE0_REG_OFFSET 0x10740
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#define CG_PLL15_CLK_RATE0_REG_OFFSET 0x10780
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#define CG_PLL16_CLK_RATE0_REG_OFFSET 0x107C0
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#endif
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