55 lines
2.0 KiB
Plaintext
55 lines
2.0 KiB
Plaintext
NXP i.MX Messaging Unit (MU)
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--------------------------------------------------------------------
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The Messaging Unit module enables two processors within the SoC to
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communicate and coordinate by passing messages (e.g. data, status
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and control) through the MU interface. The MU also provides the ability
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for one processor to signal the other processor using interrupts.
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Because the MU manages the messaging between processors, the MU uses
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different clocks (from each side of the different peripheral buses).
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Therefore, the MU must synchronize the accesses from one side to the
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other. The MU accomplishes synchronization using two sets of matching
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registers (Processor A-facing, Processor B-facing).
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Messaging Unit Device Node:
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=============================
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Required properties:
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-------------------
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- compatible : should be "fsl,<chip>-mu", the supported chips include
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imx6sx, imx7s, imx8qxp, imx8qm.
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The "fsl,imx6sx-mu" compatible is seen as generic and should
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be included together with SoC specific compatible.
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- reg : Should contain the registers location and length
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- interrupts : Interrupt number. The interrupt specifier format depends
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on the interrupt controller parent.
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- #mbox-cells: Must be 2.
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<&phandle type channel>
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phandle : Label name of controller
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type : Channel type
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channel : Channel number
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This MU support 4 type of unidirectional channels, each type
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has 4 channels. A total of 16 channels. Following types are
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supported:
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0 - TX channel with 32bit transmit register and IRQ transmit
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acknowledgment support.
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1 - RX channel with 32bit receive register and IRQ support
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2 - TX doorbell channel. Without own register and no ACK support.
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3 - RX doorbell channel.
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Optional properties:
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-------------------
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- clocks : phandle to the input clock.
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- fsl,mu-side-b : Should be set for side B MU.
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Examples:
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--------
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lsio_mu0: mailbox@5d1b0000 {
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compatible = "fsl,imx8qxp-mu";
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reg = <0x0 0x5d1b0000 0x0 0x10000>;
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <2>;
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};
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