87 lines
2.0 KiB
C
87 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014 Google, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <pch.h>
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#define GPIO_BASE 0x48
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#define IO_BASE 0x4c
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#define SBASE_ADDR 0x54
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static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
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{
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uint32_t sbase_addr;
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dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
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*sbasep = sbase_addr & 0xfffffe00;
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return 0;
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}
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static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
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{
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u32 base;
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/*
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* GPIO_BASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros.
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*
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* Note we don't need check bit0 here, because the Tunnel Creek
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* GPIO base address register bit0 is reserved (read returns 0),
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* while on the Ivybridge the bit0 is used to indicate it is an
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* I/O space.
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*/
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dm_pci_read_config32(dev, GPIO_BASE, &base);
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if (base == 0x00000000 || base == 0xffffffff) {
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debug("%s: unexpected BASE value\n", __func__);
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return -ENODEV;
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}
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/*
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* Okay, I guess we're looking at the right device. The actual
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* GPIO registers are in the PCI device's I/O space, starting
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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*gbasep = base & 1 ? base & ~3 : base & ~15;
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return 0;
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}
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static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
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{
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u32 base;
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dm_pci_read_config32(dev, IO_BASE, &base);
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if (base == 0x00000000 || base == 0xffffffff) {
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debug("%s: unexpected BASE value\n", __func__);
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return -ENODEV;
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}
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*iobasep = base & 1 ? base & ~3 : base & ~15;
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return 0;
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}
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static const struct pch_ops pch9_ops = {
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.get_spi_base = pch9_get_spi_base,
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.get_gpio_base = pch9_get_gpio_base,
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.get_io_base = pch9_get_io_base,
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};
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static const struct udevice_id pch9_ids[] = {
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{ .compatible = "intel,pch9" },
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{ }
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};
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U_BOOT_DRIVER(pch9_drv) = {
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.name = "intel-pch9",
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.id = UCLASS_PCH,
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.of_match = pch9_ids,
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.ops = &pch9_ops,
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};
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