81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* pxa_lcd.h - PXA LCD Controller structures
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*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#ifndef _PXA_LCD_H_
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#define _PXA_LCD_H_
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/*
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* PXA LCD DMA descriptor
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*/
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struct pxafb_dma_descriptor {
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u_long fdadr; /* Frame descriptor address register */
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u_long fsadr; /* Frame source address register */
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u_long fidr; /* Frame ID register */
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u_long ldcmd; /* Command register */
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};
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/*
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* PXA LCD info
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*/
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struct pxafb_info {
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/* Misc registers */
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u_long reg_lccr3;
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u_long reg_lccr2;
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u_long reg_lccr1;
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u_long reg_lccr0;
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u_long fdadr0;
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u_long fdadr1;
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/* DMA descriptors */
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struct pxafb_dma_descriptor *dmadesc_fblow;
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struct pxafb_dma_descriptor *dmadesc_fbhigh;
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struct pxafb_dma_descriptor *dmadesc_palette;
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u_long screen; /* physical address of frame buffer */
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u_long palette; /* physical address of palette memory */
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u_int palette_size;
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};
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/*
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* LCD controller stucture for PXA CPU
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*/
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typedef struct vidinfo {
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ushort vl_col; /* Number of columns (i.e. 640) */
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ushort vl_row; /* Number of rows (i.e. 480) */
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ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
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ushort vl_width; /* Width of display area in millimeters */
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ushort vl_height; /* Height of display area in millimeters */
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/* LCD configuration register */
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u_char vl_clkp; /* Clock polarity */
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u_char vl_oep; /* Output Enable polarity */
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u_char vl_hsp; /* Horizontal Sync polarity */
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u_char vl_vsp; /* Vertical Sync polarity */
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u_char vl_dp; /* Data polarity */
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u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
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u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
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u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
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u_char vl_clor; /* Color, 0 = mono, 1 = color */
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u_char vl_tft; /* 0 = passive, 1 = TFT */
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/* Horizontal control register. Timing from data sheet */
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ushort vl_hpw; /* Horz sync pulse width */
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u_char vl_blw; /* Wait before of line */
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u_char vl_elw; /* Wait end of line */
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/* Vertical control register. */
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u_char vl_vpw; /* Vertical sync pulse width */
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u_char vl_bfw; /* Wait before of frame */
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u_char vl_efw; /* Wait end of frame */
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/* PXA LCD controller params */
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struct pxafb_info pxa;
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} vidinfo_t;
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#endif
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