941 lines
40 KiB
C
941 lines
40 KiB
C
/** @file */
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#ifndef _MACH_T186_CLK_T186_H
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#define _MACH_T186_CLK_T186_H
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/**
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* @defgroup clock_ids Clock Identifiers
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* @{
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* @defgroup extern_input external input clocks
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* @{
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* @def TEGRA186_CLK_OSC
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* @def TEGRA186_CLK_CLK_32K
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* @def TEGRA186_CLK_DTV_INPUT
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* @def TEGRA186_CLK_SOR0_PAD_CLKOUT
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* @def TEGRA186_CLK_SOR1_PAD_CLKOUT
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* @def TEGRA186_CLK_I2S1_SYNC_INPUT
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* @def TEGRA186_CLK_I2S2_SYNC_INPUT
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* @def TEGRA186_CLK_I2S3_SYNC_INPUT
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* @def TEGRA186_CLK_I2S4_SYNC_INPUT
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* @def TEGRA186_CLK_I2S5_SYNC_INPUT
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* @def TEGRA186_CLK_I2S6_SYNC_INPUT
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* @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
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* @}
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*
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* @defgroup extern_output external output clocks
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* @{
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* @def TEGRA186_CLK_EXTPERIPH1
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* @def TEGRA186_CLK_EXTPERIPH2
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* @def TEGRA186_CLK_EXTPERIPH3
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* @def TEGRA186_CLK_EXTPERIPH4
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* @}
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*
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* @defgroup display_clks display related clocks
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* @{
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* @def TEGRA186_CLK_CEC
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* @def TEGRA186_CLK_DSIC
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* @def TEGRA186_CLK_DSIC_LP
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* @def TEGRA186_CLK_DSID
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* @def TEGRA186_CLK_DSID_LP
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* @def TEGRA186_CLK_DPAUX1
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* @def TEGRA186_CLK_DPAUX
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* @def TEGRA186_CLK_HDA2HDMICODEC
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* @def TEGRA186_CLK_NVDISPLAY_DISP
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* @def TEGRA186_CLK_NVDISPLAY_DSC
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* @def TEGRA186_CLK_NVDISPLAY_P0
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* @def TEGRA186_CLK_NVDISPLAY_P1
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* @def TEGRA186_CLK_NVDISPLAY_P2
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* @def TEGRA186_CLK_NVDISPLAYHUB
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* @def TEGRA186_CLK_SOR_SAFE
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* @def TEGRA186_CLK_SOR0
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* @def TEGRA186_CLK_SOR0_OUT
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* @def TEGRA186_CLK_SOR1
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* @def TEGRA186_CLK_SOR1_OUT
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* @def TEGRA186_CLK_DSI
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* @def TEGRA186_CLK_MIPI_CAL
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* @def TEGRA186_CLK_DSIA_LP
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* @def TEGRA186_CLK_DSIB
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* @def TEGRA186_CLK_DSIB_LP
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* @}
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*
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* @defgroup camera_clks camera related clocks
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* @{
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* @def TEGRA186_CLK_NVCSI
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* @def TEGRA186_CLK_NVCSILP
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* @def TEGRA186_CLK_VI
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* @}
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*
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* @defgroup audio_clks audio related clocks
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* @{
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* @def TEGRA186_CLK_ACLK
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* @def TEGRA186_CLK_ADSP
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* @def TEGRA186_CLK_ADSPNEON
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* @def TEGRA186_CLK_AHUB
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* @def TEGRA186_CLK_APE
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* @def TEGRA186_CLK_APB2APE
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* @def TEGRA186_CLK_AUD_MCLK
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* @def TEGRA186_CLK_DMIC1
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* @def TEGRA186_CLK_DMIC2
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* @def TEGRA186_CLK_DMIC3
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* @def TEGRA186_CLK_DMIC4
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* @def TEGRA186_CLK_DSPK1
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* @def TEGRA186_CLK_DSPK2
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* @def TEGRA186_CLK_HDA
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* @def TEGRA186_CLK_HDA2CODEC_2X
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* @def TEGRA186_CLK_I2S1
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* @def TEGRA186_CLK_I2S2
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* @def TEGRA186_CLK_I2S3
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* @def TEGRA186_CLK_I2S4
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* @def TEGRA186_CLK_I2S5
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* @def TEGRA186_CLK_I2S6
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* @def TEGRA186_CLK_MAUD
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* @def TEGRA186_CLK_PLL_A_OUT0
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* @def TEGRA186_CLK_SPDIF_DOUBLER
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* @def TEGRA186_CLK_SPDIF_IN
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* @def TEGRA186_CLK_SPDIF_OUT
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* @def TEGRA186_CLK_SYNC_DMIC1
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* @def TEGRA186_CLK_SYNC_DMIC2
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* @def TEGRA186_CLK_SYNC_DMIC3
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* @def TEGRA186_CLK_SYNC_DMIC4
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* @def TEGRA186_CLK_SYNC_DMIC5
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* @def TEGRA186_CLK_SYNC_DSPK1
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* @def TEGRA186_CLK_SYNC_DSPK2
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* @def TEGRA186_CLK_SYNC_I2S1
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* @def TEGRA186_CLK_SYNC_I2S2
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* @def TEGRA186_CLK_SYNC_I2S3
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* @def TEGRA186_CLK_SYNC_I2S4
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* @def TEGRA186_CLK_SYNC_I2S5
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* @def TEGRA186_CLK_SYNC_I2S6
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* @def TEGRA186_CLK_SYNC_SPDIF
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* @}
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*
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* @defgroup uart_clks UART clocks
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* @{
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* @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
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* @def TEGRA186_CLK_UARTA
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* @def TEGRA186_CLK_UARTB
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* @def TEGRA186_CLK_UARTC
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* @def TEGRA186_CLK_UARTD
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* @def TEGRA186_CLK_UARTE
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* @def TEGRA186_CLK_UARTF
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* @def TEGRA186_CLK_UARTG
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* @def TEGRA186_CLK_UART_FST_MIPI_CAL
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* @}
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*
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* @defgroup i2c_clks I2C clocks
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* @{
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* @def TEGRA186_CLK_AON_I2C_SLOW
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* @def TEGRA186_CLK_I2C1
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* @def TEGRA186_CLK_I2C2
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* @def TEGRA186_CLK_I2C3
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* @def TEGRA186_CLK_I2C4
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* @def TEGRA186_CLK_I2C5
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* @def TEGRA186_CLK_I2C6
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* @def TEGRA186_CLK_I2C8
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* @def TEGRA186_CLK_I2C9
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* @def TEGRA186_CLK_I2C1
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* @def TEGRA186_CLK_I2C12
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* @def TEGRA186_CLK_I2C13
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* @def TEGRA186_CLK_I2C14
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* @def TEGRA186_CLK_I2C_SLOW
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* @def TEGRA186_CLK_VI_I2C
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* @}
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*
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* @defgroup spi_clks SPI clocks
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* @{
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* @def TEGRA186_CLK_SPI1
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* @def TEGRA186_CLK_SPI2
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* @def TEGRA186_CLK_SPI3
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* @def TEGRA186_CLK_SPI4
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* @}
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*
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* @defgroup storage storage related clocks
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* @{
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* @def TEGRA186_CLK_SATA
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* @def TEGRA186_CLK_SATA_OOB
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* @def TEGRA186_CLK_SATA_IOBIST
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* @def TEGRA186_CLK_SDMMC_LEGACY_TM
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* @def TEGRA186_CLK_SDMMC1
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* @def TEGRA186_CLK_SDMMC2
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* @def TEGRA186_CLK_SDMMC3
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* @def TEGRA186_CLK_SDMMC4
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* @def TEGRA186_CLK_QSPI
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* @def TEGRA186_CLK_QSPI_OUT
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* @def TEGRA186_CLK_UFSDEV_REF
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* @def TEGRA186_CLK_UFSHC
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* @}
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*
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* @defgroup pwm_clks PWM clocks
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* @{
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* @def TEGRA186_CLK_PWM1
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* @def TEGRA186_CLK_PWM2
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* @def TEGRA186_CLK_PWM3
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* @def TEGRA186_CLK_PWM4
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* @def TEGRA186_CLK_PWM5
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* @def TEGRA186_CLK_PWM6
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* @def TEGRA186_CLK_PWM7
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* @def TEGRA186_CLK_PWM8
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* @}
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*
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* @defgroup plls PLLs and related clocks
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* @{
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* @def TEGRA186_CLK_PLLREFE_OUT_GATED
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* @def TEGRA186_CLK_PLLREFE_OUT1
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* @def TEGRA186_CLK_PLLD_OUT1
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* @def TEGRA186_CLK_PLLP_OUT0
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* @def TEGRA186_CLK_PLLP_OUT5
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* @def TEGRA186_CLK_PLLA
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* @def TEGRA186_CLK_PLLE_PWRSEQ
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* @def TEGRA186_CLK_PLLA_OUT1
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* @def TEGRA186_CLK_PLLREFE_REF
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* @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
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* @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
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* @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
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* @def TEGRA186_CLK_PLLREFE_PEX
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* @def TEGRA186_CLK_PLLREFE_IDDQ
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* @def TEGRA186_CLK_PLLC_OUT_AON
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* @def TEGRA186_CLK_PLLC_OUT_ISP
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* @def TEGRA186_CLK_PLLC_OUT_VE
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* @def TEGRA186_CLK_PLLC4_OUT
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* @def TEGRA186_CLK_PLLREFE_OUT
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* @def TEGRA186_CLK_PLLREFE_PLL_REF
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* @def TEGRA186_CLK_PLLE
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* @def TEGRA186_CLK_PLLC
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* @def TEGRA186_CLK_PLLP
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* @def TEGRA186_CLK_PLLD
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* @def TEGRA186_CLK_PLLD2
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* @def TEGRA186_CLK_PLLREFE_VCO
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* @def TEGRA186_CLK_PLLC2
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* @def TEGRA186_CLK_PLLC3
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* @def TEGRA186_CLK_PLLDP
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* @def TEGRA186_CLK_PLLC4_VCO
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* @def TEGRA186_CLK_PLLA1
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* @def TEGRA186_CLK_PLLNVCSI
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* @def TEGRA186_CLK_PLLDISPHUB
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* @def TEGRA186_CLK_PLLD3
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* @def TEGRA186_CLK_PLLBPMPCAM
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* @def TEGRA186_CLK_PLLAON
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* @def TEGRA186_CLK_PLLU
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* @def TEGRA186_CLK_PLLC4_VCO_DIV2
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* @def TEGRA186_CLK_PLL_REF
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* @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
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* @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
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* @def TEGRA186_CLK_PLL_U_48M
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* @def TEGRA186_CLK_PLL_U_480M
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* @def TEGRA186_CLK_PLLC4_OUT0
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* @def TEGRA186_CLK_PLLC4_OUT1
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* @def TEGRA186_CLK_PLLC4_OUT2
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* @def TEGRA186_CLK_PLLC4_OUT_MUX
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* @def TEGRA186_CLK_DFLLDISP_DIV
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* @def TEGRA186_CLK_PLLDISPHUB_DIV
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* @def TEGRA186_CLK_PLLP_DIV8
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* @}
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*
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* @defgroup nafll_clks NAFLL clock sources
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* @{
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* @def TEGRA186_CLK_NAFLL_AXI_CBB
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* @def TEGRA186_CLK_NAFLL_BCPU
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* @def TEGRA186_CLK_NAFLL_BPMP
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* @def TEGRA186_CLK_NAFLL_DISP
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* @def TEGRA186_CLK_NAFLL_GPU
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* @def TEGRA186_CLK_NAFLL_ISP
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* @def TEGRA186_CLK_NAFLL_MCPU
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* @def TEGRA186_CLK_NAFLL_NVDEC
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* @def TEGRA186_CLK_NAFLL_NVENC
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* @def TEGRA186_CLK_NAFLL_NVJPG
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* @def TEGRA186_CLK_NAFLL_SCE
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* @def TEGRA186_CLK_NAFLL_SE
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* @def TEGRA186_CLK_NAFLL_TSEC
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* @def TEGRA186_CLK_NAFLL_TSECB
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* @def TEGRA186_CLK_NAFLL_VI
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* @def TEGRA186_CLK_NAFLL_VIC
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* @}
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*
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* @defgroup mphy MPHY related clocks
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* @{
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* @def TEGRA186_CLK_MPHY_L0_RX_SYMB
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* @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
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* @def TEGRA186_CLK_MPHY_L0_TX_SYMB
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* @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
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* @def TEGRA186_CLK_MPHY_L0_RX_ANA
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* @def TEGRA186_CLK_MPHY_L1_RX_ANA
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* @def TEGRA186_CLK_MPHY_IOBIST
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* @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
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* @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
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* @}
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*
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* @defgroup eavb EAVB related clocks
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* @{
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* @def TEGRA186_CLK_EQOS_AXI
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* @def TEGRA186_CLK_EQOS_PTP_REF
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* @def TEGRA186_CLK_EQOS_RX
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* @def TEGRA186_CLK_EQOS_RX_INPUT
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* @def TEGRA186_CLK_EQOS_TX
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* @}
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*
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* @defgroup usb USB related clocks
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* @{
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* @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
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* @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
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* @def TEGRA186_CLK_HSIC_TRK
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* @def TEGRA186_CLK_USB2_TRK
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* @def TEGRA186_CLK_USB2_HSIC_TRK
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* @def TEGRA186_CLK_XUSB_CORE_SS
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* @def TEGRA186_CLK_XUSB_CORE_DEV
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* @def TEGRA186_CLK_XUSB_FALCON
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* @def TEGRA186_CLK_XUSB_FS
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* @def TEGRA186_CLK_XUSB
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* @def TEGRA186_CLK_XUSB_DEV
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* @def TEGRA186_CLK_XUSB_HOST
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* @def TEGRA186_CLK_XUSB_SS
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* @}
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*
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* @defgroup bigblock compute block related clocks
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* @{
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* @def TEGRA186_CLK_GPCCLK
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* @def TEGRA186_CLK_GPC2CLK
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* @def TEGRA186_CLK_GPU
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* @def TEGRA186_CLK_HOST1X
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* @def TEGRA186_CLK_ISP
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* @def TEGRA186_CLK_NVDEC
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* @def TEGRA186_CLK_NVENC
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* @def TEGRA186_CLK_NVJPG
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* @def TEGRA186_CLK_SE
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* @def TEGRA186_CLK_TSEC
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* @def TEGRA186_CLK_TSECB
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* @def TEGRA186_CLK_VIC
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* @}
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*
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* @defgroup can CAN bus related clocks
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* @{
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* @def TEGRA186_CLK_CAN1
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* @def TEGRA186_CLK_CAN1_HOST
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* @def TEGRA186_CLK_CAN2
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* @def TEGRA186_CLK_CAN2_HOST
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* @}
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*
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* @defgroup system basic system clocks
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* @{
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* @def TEGRA186_CLK_ACTMON
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* @def TEGRA186_CLK_AON_APB
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* @def TEGRA186_CLK_AON_CPU_NIC
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* @def TEGRA186_CLK_AON_NIC
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* @def TEGRA186_CLK_AXI_CBB
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* @def TEGRA186_CLK_BPMP_APB
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* @def TEGRA186_CLK_BPMP_CPU_NIC
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* @def TEGRA186_CLK_BPMP_NIC_RATE
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* @def TEGRA186_CLK_CLK_M
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* @def TEGRA186_CLK_EMC
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* @def TEGRA186_CLK_MSS_ENCRYPT
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* @def TEGRA186_CLK_SCE_APB
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* @def TEGRA186_CLK_SCE_CPU_NIC
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* @def TEGRA186_CLK_SCE_NIC
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* @def TEGRA186_CLK_TSC
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* @}
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*
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* @defgroup pcie_clks PCIe related clocks
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* @{
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* @def TEGRA186_CLK_AFI
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* @def TEGRA186_CLK_PCIE
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* @def TEGRA186_CLK_PCIE2_IOBIST
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* @def TEGRA186_CLK_PCIERX0
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* @def TEGRA186_CLK_PCIERX1
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* @def TEGRA186_CLK_PCIERX2
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* @def TEGRA186_CLK_PCIERX3
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* @def TEGRA186_CLK_PCIERX4
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* @}
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*/
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/** @brief output of gate CLK_ENB_FUSE */
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#define TEGRA186_CLK_FUSE 0
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/**
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* @brief It's not what you think
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* @details output of gate CLK_ENB_GPU. This output connects to the GPU
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* pwrclk. @warning: This is almost certainly not the clock you think
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* it is. If you're looking for the clock of the graphics engine, see
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* TEGRA186_GPCCLK
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*/
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#define TEGRA186_CLK_GPU 1
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/** @brief output of gate CLK_ENB_PCIE */
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#define TEGRA186_CLK_PCIE 3
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/** @brief output of the divider IPFS_CLK_DIVISOR */
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#define TEGRA186_CLK_AFI 4
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/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
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#define TEGRA186_CLK_PCIE2_IOBIST 5
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/** @brief output of gate CLK_ENB_PCIERX0*/
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#define TEGRA186_CLK_PCIERX0 6
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/** @brief output of gate CLK_ENB_PCIERX1*/
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#define TEGRA186_CLK_PCIERX1 7
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/** @brief output of gate CLK_ENB_PCIERX2*/
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#define TEGRA186_CLK_PCIERX2 8
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/** @brief output of gate CLK_ENB_PCIERX3*/
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#define TEGRA186_CLK_PCIERX3 9
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/** @brief output of gate CLK_ENB_PCIERX4*/
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#define TEGRA186_CLK_PCIERX4 10
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/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
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#define TEGRA186_CLK_PLLC_OUT_ISP 11
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/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
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#define TEGRA186_CLK_PLLC_OUT_VE 12
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/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
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#define TEGRA186_CLK_PLLC_OUT_AON 13
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/** @brief output of gate CLK_ENB_SOR_SAFE */
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#define TEGRA186_CLK_SOR_SAFE 39
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
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#define TEGRA186_CLK_I2S2 42
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
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#define TEGRA186_CLK_I2S3 43
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
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#define TEGRA186_CLK_SPDIF_IN 44
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/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
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#define TEGRA186_CLK_SPDIF_DOUBLER 45
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/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
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#define TEGRA186_CLK_SPI3 46
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/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
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#define TEGRA186_CLK_I2C1 47
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/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
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#define TEGRA186_CLK_I2C5 48
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
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#define TEGRA186_CLK_SPI1 49
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
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#define TEGRA186_CLK_ISP 50
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
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#define TEGRA186_CLK_VI 51
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
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#define TEGRA186_CLK_SDMMC1 52
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
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#define TEGRA186_CLK_SDMMC2 53
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
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#define TEGRA186_CLK_SDMMC4 54
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
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#define TEGRA186_CLK_UARTA 55
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
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#define TEGRA186_CLK_UARTB 56
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
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#define TEGRA186_CLK_HOST1X 57
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/**
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* @brief controls the EMC clock frequency.
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* @details Doing a clk_set_rate on this clock will select the
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* appropriate clock source, program the source rate and execute a
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* specific sequence to switch to the new clock source for both memory
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* controllers. This can be used to control the balance between memory
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* throughput and memory controller power.
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*/
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#define TEGRA186_CLK_EMC 58
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/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
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#define TEGRA186_CLK_EXTPERIPH4 73
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
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#define TEGRA186_CLK_SPI4 74
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
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#define TEGRA186_CLK_I2C3 75
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
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#define TEGRA186_CLK_SDMMC3 76
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
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#define TEGRA186_CLK_UARTD 77
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
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#define TEGRA186_CLK_I2S1 79
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/** output of gate CLK_ENB_DTV */
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#define TEGRA186_CLK_DTV 80
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
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#define TEGRA186_CLK_TSEC 81
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/** @brief output of gate CLK_ENB_DP2 */
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#define TEGRA186_CLK_DP2 82
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
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#define TEGRA186_CLK_I2S4 84
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
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#define TEGRA186_CLK_I2S5 85
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
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#define TEGRA186_CLK_I2C4 86
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
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#define TEGRA186_CLK_AHUB 87
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
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#define TEGRA186_CLK_HDA2CODEC_2X 88
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
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#define TEGRA186_CLK_EXTPERIPH1 89
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
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#define TEGRA186_CLK_EXTPERIPH2 90
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
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#define TEGRA186_CLK_EXTPERIPH3 91
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
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#define TEGRA186_CLK_I2C_SLOW 92
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/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
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#define TEGRA186_CLK_SOR1 93
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/** @brief output of gate CLK_ENB_CEC */
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#define TEGRA186_CLK_CEC 94
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/** @brief output of gate CLK_ENB_DPAUX1 */
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#define TEGRA186_CLK_DPAUX1 95
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/** @brief output of gate CLK_ENB_DPAUX */
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#define TEGRA186_CLK_DPAUX 96
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/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
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#define TEGRA186_CLK_SOR0 97
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/** @brief output of gate CLK_ENB_HDA2HDMICODEC */
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#define TEGRA186_CLK_HDA2HDMICODEC 98
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
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#define TEGRA186_CLK_SATA 99
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/** @brief output of gate CLK_ENB_SATA_OOB */
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#define TEGRA186_CLK_SATA_OOB 100
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/** @brief output of gate CLK_ENB_SATA_IOBIST */
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#define TEGRA186_CLK_SATA_IOBIST 101
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
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#define TEGRA186_CLK_HDA 102
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
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#define TEGRA186_CLK_SE 103
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/** @brief output of gate CLK_ENB_APB2APE */
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#define TEGRA186_CLK_APB2APE 104
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
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#define TEGRA186_CLK_APE 105
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/** @brief output of gate CLK_ENB_IQC1 */
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#define TEGRA186_CLK_IQC1 106
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/** @brief output of gate CLK_ENB_IQC2 */
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#define TEGRA186_CLK_IQC2 107
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/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
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#define TEGRA186_CLK_PLLREFE_OUT 108
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/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
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#define TEGRA186_CLK_PLLREFE_PLL_REF 109
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/** @brief output of gate CLK_ENB_PLLC4_OUT */
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#define TEGRA186_CLK_PLLC4_OUT 110
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/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB 111
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/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_DEV 112
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/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_HOST 113
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/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_SS 114
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/** @brief output of gate CLK_ENB_DSI */
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#define TEGRA186_CLK_DSI 115
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/** @brief output of gate CLK_ENB_MIPI_CAL */
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#define TEGRA186_CLK_MIPI_CAL 116
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
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#define TEGRA186_CLK_DSIA_LP 117
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/** @brief output of gate CLK_ENB_DSIB */
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#define TEGRA186_CLK_DSIB 118
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
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#define TEGRA186_CLK_DSIB_LP 119
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
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#define TEGRA186_CLK_DMIC1 122
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
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#define TEGRA186_CLK_DMIC2 123
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
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#define TEGRA186_CLK_AUD_MCLK 124
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
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#define TEGRA186_CLK_I2C6 125
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/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
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#define TEGRA186_CLK_UART_FST_MIPI_CAL 126
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
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#define TEGRA186_CLK_VIC 127
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
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#define TEGRA186_CLK_SDMMC_LEGACY_TM 128
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
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#define TEGRA186_CLK_NVDEC 129
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
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#define TEGRA186_CLK_NVJPG 130
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
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#define TEGRA186_CLK_NVENC 131
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/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
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#define TEGRA186_CLK_QSPI 132
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
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#define TEGRA186_CLK_VI_I2C 133
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/** @brief output of gate CLK_ENB_HSIC_TRK */
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#define TEGRA186_CLK_HSIC_TRK 134
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/** @brief output of gate CLK_ENB_USB2_TRK */
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#define TEGRA186_CLK_USB2_TRK 135
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/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
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#define TEGRA186_CLK_MAUD 136
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
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#define TEGRA186_CLK_TSECB 137
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/** @brief output of gate CLK_ENB_ADSP */
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#define TEGRA186_CLK_ADSP 138
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/** @brief output of gate CLK_ENB_ADSPNEON */
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#define TEGRA186_CLK_ADSPNEON 139
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
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#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
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/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
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#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
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#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
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/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
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#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
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/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
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#define TEGRA186_CLK_MPHY_L0_RX_ANA 144
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/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
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#define TEGRA186_CLK_MPHY_L1_RX_ANA 145
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
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#define TEGRA186_CLK_MPHY_IOBIST 146
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
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#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
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#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
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#define TEGRA186_CLK_AXI_CBB 149
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
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#define TEGRA186_CLK_DMIC3 150
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
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#define TEGRA186_CLK_DMIC4 151
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
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#define TEGRA186_CLK_DSPK1 152
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
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#define TEGRA186_CLK_DSPK2 153
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
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#define TEGRA186_CLK_I2S6 154
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
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#define TEGRA186_CLK_NVDISPLAY_P0 155
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/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
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#define TEGRA186_CLK_NVDISPLAY_DISP 156
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/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
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#define TEGRA186_CLK_NVDISPLAY_DSC 157
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
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#define TEGRA186_CLK_NVDISPLAYHUB 158
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
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#define TEGRA186_CLK_NVDISPLAY_P1 159
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
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#define TEGRA186_CLK_NVDISPLAY_P2 160
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
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#define TEGRA186_CLK_TACH 166
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/** @brief output of gate CLK_ENB_EQOS */
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#define TEGRA186_CLK_EQOS_AXI 167
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/** @brief output of gate CLK_ENB_EQOS_RX */
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#define TEGRA186_CLK_EQOS_RX 168
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
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#define TEGRA186_CLK_UFSHC 178
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
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#define TEGRA186_CLK_UFSDEV_REF 179
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
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#define TEGRA186_CLK_NVCSI 180
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
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#define TEGRA186_CLK_NVCSILP 181
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
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#define TEGRA186_CLK_I2C7 182
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
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#define TEGRA186_CLK_I2C9 183
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
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#define TEGRA186_CLK_I2C12 184
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
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#define TEGRA186_CLK_I2C13 185
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
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#define TEGRA186_CLK_I2C14 186
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
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#define TEGRA186_CLK_PWM1 187
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
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#define TEGRA186_CLK_PWM2 188
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
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#define TEGRA186_CLK_PWM3 189
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
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#define TEGRA186_CLK_PWM5 190
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
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#define TEGRA186_CLK_PWM6 191
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
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|
#define TEGRA186_CLK_PWM7 192
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
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#define TEGRA186_CLK_PWM8 193
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
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#define TEGRA186_CLK_UARTE 194
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
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#define TEGRA186_CLK_UARTF 195
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|
/** @deprecated */
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|
#define TEGRA186_CLK_DBGAPB 196
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
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|
#define TEGRA186_CLK_BPMP_CPU_NIC 197
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
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|
#define TEGRA186_CLK_BPMP_APB 199
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/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
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|
#define TEGRA186_CLK_ACTMON 201
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
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|
#define TEGRA186_CLK_AON_CPU_NIC 208
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
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|
#define TEGRA186_CLK_CAN1 210
|
|
/** @brief output of gate CLK_ENB_CAN1_HOST */
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|
#define TEGRA186_CLK_CAN1_HOST 211
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
|
|
#define TEGRA186_CLK_CAN2 212
|
|
/** @brief output of gate CLK_ENB_CAN2_HOST */
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|
#define TEGRA186_CLK_CAN2_HOST 213
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
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|
#define TEGRA186_CLK_AON_APB 214
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
|
|
#define TEGRA186_CLK_UARTC 215
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
|
|
#define TEGRA186_CLK_UARTG 216
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
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|
#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
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#define TEGRA186_CLK_I2C2 218
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
|
|
#define TEGRA186_CLK_I2C8 219
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
|
|
#define TEGRA186_CLK_I2C10 220
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
|
|
#define TEGRA186_CLK_AON_I2C_SLOW 221
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
|
|
#define TEGRA186_CLK_SPI2 222
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
|
|
#define TEGRA186_CLK_DMIC5 223
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
|
|
#define TEGRA186_CLK_AON_TOUCH 224
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
|
|
#define TEGRA186_CLK_PWM4 225
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
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|
#define TEGRA186_CLK_TSC 226
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
|
|
#define TEGRA186_CLK_MSS_ENCRYPT 227
|
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
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#define TEGRA186_CLK_SCE_CPU_NIC 228
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
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#define TEGRA186_CLK_SCE_APB 230
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|
/** @brief output of gate CLK_ENB_DSIC */
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#define TEGRA186_CLK_DSIC 231
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
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#define TEGRA186_CLK_DSIC_LP 232
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|
/** @brief output of gate CLK_ENB_DSID */
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#define TEGRA186_CLK_DSID 233
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|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
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#define TEGRA186_CLK_DSID_LP 234
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
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#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
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#define TEGRA186_CLK_SPDIF_OUT 238
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
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#define TEGRA186_CLK_EQOS_PTP_REF 239
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
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#define TEGRA186_CLK_EQOS_TX 240
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
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#define TEGRA186_CLK_USB2_HSIC_TRK 241
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/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_CORE_SS 242
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/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_CORE_DEV 243
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/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_FALCON 244
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/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
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#define TEGRA186_CLK_XUSB_FS 245
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
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#define TEGRA186_CLK_PLL_A_OUT0 246
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
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#define TEGRA186_CLK_SYNC_I2S1 247
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
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#define TEGRA186_CLK_SYNC_I2S2 248
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
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#define TEGRA186_CLK_SYNC_I2S3 249
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
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#define TEGRA186_CLK_SYNC_I2S4 250
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
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#define TEGRA186_CLK_SYNC_I2S5 251
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
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#define TEGRA186_CLK_SYNC_I2S6 252
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
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#define TEGRA186_CLK_SYNC_DSPK1 253
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
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#define TEGRA186_CLK_SYNC_DSPK2 254
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
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#define TEGRA186_CLK_SYNC_DMIC1 255
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
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#define TEGRA186_CLK_SYNC_DMIC2 256
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
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#define TEGRA186_CLK_SYNC_DMIC3 257
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
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#define TEGRA186_CLK_SYNC_DMIC4 259
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
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#define TEGRA186_CLK_SYNC_SPDIF 260
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/** @brief output of gate CLK_ENB_PLLREFE_OUT */
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#define TEGRA186_CLK_PLLREFE_OUT_GATED 261
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/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
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* * VCO/pdiv defined by this clock object
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* * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
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|
*/
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#define TEGRA186_CLK_PLLREFE_OUT1 262
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#define TEGRA186_CLK_PLLD_OUT1 267
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/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
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#define TEGRA186_CLK_PLLP_OUT0 269
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
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#define TEGRA186_CLK_PLLP_OUT5 270
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/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
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#define TEGRA186_CLK_PLLA 271
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/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
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#define TEGRA186_CLK_ACLK 273
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/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
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#define TEGRA186_CLK_PLL_U_48M 274
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|
/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
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#define TEGRA186_CLK_PLL_U_480M 275
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|
/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
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#define TEGRA186_CLK_PLLC4_OUT0 276
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/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
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#define TEGRA186_CLK_PLLC4_OUT1 277
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/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
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#define TEGRA186_CLK_PLLC4_OUT2 278
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/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
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#define TEGRA186_CLK_PLLC4_OUT_MUX 279
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/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
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#define TEGRA186_CLK_DFLLDISP_DIV 284
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/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
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#define TEGRA186_CLK_PLLDISPHUB_DIV 285
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/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
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#define TEGRA186_CLK_PLLP_DIV8 286
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/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
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#define TEGRA186_CLK_BPMP_NIC 287
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/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
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#define TEGRA186_CLK_PLL_A_OUT1 288
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/** @deprecated */
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#define TEGRA186_CLK_GPC2CLK 289
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/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
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#define TEGRA186_CLK_KFUSE 293
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/**
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* @brief controls the PLLE hardware sequencer.
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* @details This clock only has enable and disable methods. When the
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* PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
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* hw based on the control signals from the PCIe, SATA and XUSB
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* clocks. When the PLLE hw sequencer is disabled, the state of PLLE
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* is controlled by sw using clk_enable/clk_disable on
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* TEGRA186_CLK_PLLE.
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|
*/
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#define TEGRA186_CLK_PLLE_PWRSEQ 294
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/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
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#define TEGRA186_CLK_PLLREFE_REF 295
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/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
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#define TEGRA186_CLK_SOR0_OUT 296
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|
/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
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#define TEGRA186_CLK_SOR1_OUT 297
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|
/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
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#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
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|
/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
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#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
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/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
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#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
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|
/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
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#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
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|
/** @brief controls the UPHY_PLL0 hardware sqeuencer */
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#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
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/** @brief controls the UPHY_PLL1 hardware sqeuencer */
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#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
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/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
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#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
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|
/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
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#define TEGRA186_CLK_PLLREFE_PEX 307
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|
/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
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#define TEGRA186_CLK_PLLREFE_IDDQ 308
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|
/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
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#define TEGRA186_CLK_QSPI_OUT 309
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/**
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* @brief GPC2CLK-div-2
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|
* @details fixed /2 divider. Output frequency is
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|
* TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
|
|
* frequency at which the GPU graphics engine runs. */
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#define TEGRA186_CLK_GPCCLK 310
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|
/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
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#define TEGRA186_CLK_AON_NIC 450
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/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
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#define TEGRA186_CLK_SCE_NIC 451
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|
/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
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|
#define TEGRA186_CLK_PLLE 512
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
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|
#define TEGRA186_CLK_PLLC 513
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|
/** Fixed 408MHz PLL for use by peripheral clocks */
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|
#define TEGRA186_CLK_PLLP 516
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|
/** @deprecated */
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|
#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
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|
#define TEGRA186_CLK_PLLD 518
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
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|
#define TEGRA186_CLK_PLLD2 519
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|
/**
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|
* @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
|
|
* @details Note that this clock only controls the VCO output, before
|
|
* the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
|
|
* information.
|
|
*/
|
|
#define TEGRA186_CLK_PLLREFE_VCO 520
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
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|
#define TEGRA186_CLK_PLLC2 521
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
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|
#define TEGRA186_CLK_PLLC3 522
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|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
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|
#define TEGRA186_CLK_PLLDP 523
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
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|
#define TEGRA186_CLK_PLLC4_VCO 524
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
|
|
#define TEGRA186_CLK_PLLA1 525
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
|
|
#define TEGRA186_CLK_PLLNVCSI 526
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
|
|
#define TEGRA186_CLK_PLLDISPHUB 527
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
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|
#define TEGRA186_CLK_PLLD3 528
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
|
|
#define TEGRA186_CLK_PLLBPMPCAM 531
|
|
/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
|
|
#define TEGRA186_CLK_PLLAON 532
|
|
/** Fixed frequency 960MHz PLL for USB and EAVB */
|
|
#define TEGRA186_CLK_PLLU 533
|
|
/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
|
|
#define TEGRA186_CLK_PLLC4_VCO_DIV2 535
|
|
/** @brief NAFLL clock source for AXI_CBB */
|
|
#define TEGRA186_CLK_NAFLL_AXI_CBB 564
|
|
/** @brief NAFLL clock source for BPMP */
|
|
#define TEGRA186_CLK_NAFLL_BPMP 565
|
|
/** @brief NAFLL clock source for ISP */
|
|
#define TEGRA186_CLK_NAFLL_ISP 566
|
|
/** @brief NAFLL clock source for NVDEC */
|
|
#define TEGRA186_CLK_NAFLL_NVDEC 567
|
|
/** @brief NAFLL clock source for NVENC */
|
|
#define TEGRA186_CLK_NAFLL_NVENC 568
|
|
/** @brief NAFLL clock source for NVJPG */
|
|
#define TEGRA186_CLK_NAFLL_NVJPG 569
|
|
/** @brief NAFLL clock source for SCE */
|
|
#define TEGRA186_CLK_NAFLL_SCE 570
|
|
/** @brief NAFLL clock source for SE */
|
|
#define TEGRA186_CLK_NAFLL_SE 571
|
|
/** @brief NAFLL clock source for TSEC */
|
|
#define TEGRA186_CLK_NAFLL_TSEC 572
|
|
/** @brief NAFLL clock source for TSECB */
|
|
#define TEGRA186_CLK_NAFLL_TSECB 573
|
|
/** @brief NAFLL clock source for VI */
|
|
#define TEGRA186_CLK_NAFLL_VI 574
|
|
/** @brief NAFLL clock source for VIC */
|
|
#define TEGRA186_CLK_NAFLL_VIC 575
|
|
/** @brief NAFLL clock source for DISP */
|
|
#define TEGRA186_CLK_NAFLL_DISP 576
|
|
/** @brief NAFLL clock source for GPU */
|
|
#define TEGRA186_CLK_NAFLL_GPU 577
|
|
/** @brief NAFLL clock source for M-CPU cluster */
|
|
#define TEGRA186_CLK_NAFLL_MCPU 578
|
|
/** @brief NAFLL clock source for B-CPU cluster */
|
|
#define TEGRA186_CLK_NAFLL_BCPU 579
|
|
/** @brief input from Tegra's CLK_32K_IN pad */
|
|
#define TEGRA186_CLK_CLK_32K 608
|
|
/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
|
|
#define TEGRA186_CLK_CLK_M 609
|
|
/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
|
|
#define TEGRA186_CLK_PLL_REF 610
|
|
/** @brief input from Tegra's XTAL_IN */
|
|
#define TEGRA186_CLK_OSC 612
|
|
/** @brief clock recovered from EAVB input */
|
|
#define TEGRA186_CLK_EQOS_RX_INPUT 613
|
|
/** @brief clock recovered from DTV input */
|
|
#define TEGRA186_CLK_DTV_INPUT 614
|
|
/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
|
|
#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
|
|
/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
|
|
#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
|
|
/** @brief clock recovered from I2S1 input */
|
|
#define TEGRA186_CLK_I2S1_SYNC_INPUT 617
|
|
/** @brief clock recovered from I2S2 input */
|
|
#define TEGRA186_CLK_I2S2_SYNC_INPUT 618
|
|
/** @brief clock recovered from I2S3 input */
|
|
#define TEGRA186_CLK_I2S3_SYNC_INPUT 619
|
|
/** @brief clock recovered from I2S4 input */
|
|
#define TEGRA186_CLK_I2S4_SYNC_INPUT 620
|
|
/** @brief clock recovered from I2S5 input */
|
|
#define TEGRA186_CLK_I2S5_SYNC_INPUT 621
|
|
/** @brief clock recovered from I2S6 input */
|
|
#define TEGRA186_CLK_I2S6_SYNC_INPUT 622
|
|
/** @brief clock recovered from SPDIFIN input */
|
|
#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
|
|
|
|
/**
|
|
* @brief subject to change
|
|
* @details maximum clock identifier value plus one.
|
|
*/
|
|
#define TEGRA186_CLK_CLK_MAX 624
|
|
|
|
/** @} */
|
|
|
|
#endif
|