442 lines
17 KiB
C
Executable File
442 lines
17 KiB
C
Executable File
/**
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@file NAND.h
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@ingroup mIDrvStg_NAND
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@brief Nand flash driver export variables and function prototypes.
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Copyright Novatek Microelectronics Corp. 2012. All rights reserved.
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*/
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#ifndef _NAND_H
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#define _NAND_H
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#ifndef _NAND2_SUPPORT_
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#define _NAND2_SUPPORT_ 1
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#endif
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#include "strg_def.h"
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/**
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@addtogroup mIDrvStg_NAND
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*/
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//@{
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//------------------------------------------------------------------------------
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// compatible with earily code base
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//------------------------------------------------------------------------------
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/**
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@name Backward compatible APIs
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For old version NAND driver
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*/
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//@{
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#define EraseAllNANDBlockMaping() nand_eraseAllPartitionBlockMapping(FALSE, FALSE, FALSE)
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//@}
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#if defined(_NVT_FPGA_)
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#define NAND_SRC_CLK 48000000
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#else
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#define NAND_SRC_CLK 480000000
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#endif
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#define PLL_CLKSEL_NAND_48 0x9
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//#define PLL_CLKSEL_NAND_60 0x7
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#define PLL_CLKSEL_NAND_80 0x5
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#define PLL_CLKSEL_NAND_96 0x4
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#define PLL_CLKSEL_NAND_120 0x3
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// -----------------------------------------------------------------------------
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// NAND driver error code
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// -----------------------------------------------------------------------------
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//
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#define NAND_ERROR_OK 0x00000000
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#define NAND_ERROR_INSUFFICIENT_FREE_BLOCK 0x00010000
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#define NAND_ERROR_TOO_MANY_BAD_UNITS 0x00080000 //Too many bad blocks result in write protection rasen.(write and erase is prohibited)
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#define NAND_ERROR_DATA_STATUS 0x00000001 //Data status is corrupt
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#define NAND_ERROR_ECC_FIELD1 0x00000002
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#define NAND_ERROR_ECC_FIELD2 0x00000004
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#define NAND_ERROR_DOUBLE_MAPPING 0x00000008
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#define NAND_ERROR_UNCORRECT_ECC 0x00000080
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#define NAND_ERROR_READ_ERROR 0x00000010
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#define NAND_ERROR_WRITE_ERROR 0x00000020
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#define NAND_ERROR_DEVICE_ERROR 0x00000040
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/**
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NAND write one reserved block param
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*/
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typedef struct {
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UINT32 uiLogicBlock;
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UINT32 uiPhysicalBlock;
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} NAND_WRITERSVCFG, *PNAND_WRITERSVCFG;
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/**
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NOR read non-blocking param
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*/
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typedef struct {
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UINT32 uiSectorAddr;
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UINT32 uiSectorSize;
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UINT8 *pBuf;
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} NOR_READ_NONBLK_CFG, *PNOR_READ_NONBLK_CFG;
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/*
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NAND specific operation condition definition
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\n Some condition can not process anytime. Need turn on/off flag
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@note for nand_setFeature(), nand_getFeature()
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*/
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typedef enum {
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NAND_ERASE_LOADER, //< TRUE: valid for erasing loader area
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NAND_ERASE_FW, //< TRUE: valid for erasing FW area
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NAND_ERASE_PSTORE, //< TRUE: valid for erasing Pstore area
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NAND_MARK_PSTORE, //< TRUE: valid for mark bad block at Pstore area
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ENUM_DUMMY4WORD(NAND_FEATRUE)
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} NAND_FEATRUE;
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/**
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SPIFLASH operation
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@note For SPIFLASH_INVALID_WRITE_CB()
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*/
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typedef enum {
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SPIFLASH_OPERATION_READ, ///< read operation
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SPIFLASH_OPERATION_WRITE, ///< write operation
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SPIFLASH_OPERATION_ERASE, ///< erase operation
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ENUM_DUMMY4WORD(SPIFLASH_OPERATION)
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} SPIFLASH_OPERATION;
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/**
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SPIFLASH invalid write callback
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Callback routine to be invoked when invalid erase/write access is detected by driver.
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@note STRG_EXT_CMD_SPI_INVALID_WRITE_CB
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@param[in] first parameter Operating type
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- @b SPIFLASH_OPERATION_ERASE: erase
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- @b SPIFLASH_OPERATION_WRITE: write
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@param[in] second parameter Starting address
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@param[in] third parameter Access length
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@return void
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*/
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typedef void (*SPIFLASH_INVALID_WRITE_CB)(SPIFLASH_OPERATION, unsigned int, unsigned int);
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extern PSTORAGE_OBJ spiflash_getStorageObject(STRG_OBJ_ID strgObjID);
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/**
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NAND configuration identifier
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@note For nand_setConfig()
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*/
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typedef enum {
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NAND_CONFIG_ID_FREQ, ///< NAND module clock (Unit: MHz), MUST config before storage object open, active after open
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///< Context can be one of the following:
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///< - @b 48 : 48 MHz (Default value)
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///< - @b 60 : 60 MHz
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///< - @b 96 : 96 MHz
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NAND_CONFIG_ID_TIMING0, ///< NAND controller timing0 register, MUST config before storage object open and need config timing1 at the same time
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///< Context is UINT32 value
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NAND_CONFIG_ID_TIMING1, ///< NAND controller timing1 register, MUST config before storage object open and need config timing0 at the same time
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///< Context is UINT32 value
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NAND_CONFIG_ID_DELAY_LATCH, ///< Context can be one of the following:
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///< - @b TRUE : 0.5T delay latch
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///< - @b FALSE : 0.0T delay latch
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///< @note: TRUE equal to 0.5 tRP
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NAND_CONFIG_ID_SET_INTEN, ///< Context can be one of the following:
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///< - @b TRUE : Enable interrupt mode
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///< - @b FALSE : Disable interrupt mode
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///< @note: Need config before any access of storage object hook on NAND device open\n
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///< such as STRG_SET_PARTITION_SIZE, STRG_SET_PARTITION_RSV_SIZE, \n
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///< STRG_GET_BEST_ACCESS_SIZE, STRG_GET_SECTOR_SIZE, STRG_GET_DEVICE_PHY_SIZE,\n
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///< STRG_GET_MEMORY_SIZE_REQ
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///< @code
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/// if(nand_setConfig(NAND_CONFIG_ID_SET_INTEN, TRUE) != E_OK)
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/// {
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/// ERROR;
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/// }
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/// //Enable Interrupt mode
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// if(nand_setConfig(NAND_CONFIG_ID_SET_INTEN, FALSE) != E_OK)
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/// {
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/// ERROR;
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/// }
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/// //Disable Interrupt mode
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/// }
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/// @endcode
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NAND_CONFIG_ID_AUTOPINMUX, ///< Context can be one of the following:
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///< - @b TRUE : disable pinmux when NAND driver close
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///< - @b FALSE : not disable pinmux when NAND driver close
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NAND_CONFIG_ID_NAND_TYPE, ///< Context can be one of the following:
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///< - @b NANDCTRL_ONFI_NAND_TYPE : ONFI NAND via NAND controller
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///< - @b NANDCTRL_SPI_NAND_TYPE : SPI NAND via NAND controller
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///< - @b NANDCTRL_SPI_NOR_TYPE : SPI NOR via NAND controller
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///< - @b SPICTRL_SPI_NAND_TYPE : SPI NAND via SPI controller
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NAND_CONFIG_ID_SPI_ECC_TYPE, ///< Context can be one of the following(only available when device is SPI NAND flash):
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///< - @b NANDCTRL_SPIFLASH_USE_INTERNAL_RS_ECC : SPI NAND use nand controller reedsolomon ecc
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///< - @b NANDCTRL_SPIFLASH_USE_ONDIE_ECC : SPI NAND use nand on die ecc(depend on each spi nand flash)
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NAND_CONFIG_ID_SPI_SEC_ECC_EN, ///< Context can be one of the following(only available when device is SPI NAND flash):
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///< - @b TRUE : Secondary ECC enable(only available when NAND_CONFIG_ID_SPI_ECC_TYPE = NANDCTRL_SPIFLASH_USE_INTERNAL_RS_ECC)
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///< - @b FALSE : Secondary ECC disable
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NAND_CONFIG_ID_SPI_OPERATION_BIT_MODE, ///< Context can be one of the following(only available when device is SPI NAND flash):
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///< - @b NANDCTRL_SPIFLASH_USE_1_BIT : SPI NAND 1 bit operation mode
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///< - @b NANDCTRL_SPIFLASH_USE_2_BIT : SPI NAND 2 bit operation mode(dual mode)
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///< - @b NANDCTRL_SPIFLASH_USE_4_BIT : SPI NAND 4 bit operation mode(quad mode)
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NAND_CONFIG_ID_NOR_TYPE, ///< Context can be one of the following:
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///< - @b NANDCTRL_SDR_TYPE : SDR mode for SPI NOR
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///< - @b NANDCTRL_DRR_TYPE : DTR mode for SPI NOR
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ENUM_DUMMY4WORD(NAND_CONFIG_ID)
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} NAND_CONFIG_ID;
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typedef enum {
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NANDCTRL_ONFI_NAND_TYPE = 0x0,
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NANDCTRL_SPI_NAND_TYPE,
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NANDCTRL_SPI_NOR_TYPE,
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SPICTRL_SPI_NAND_TYPE,
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NAND_TYPE_NUM,
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ENUM_DUMMY4WORD(NAND_TYPE_SEL)
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} NAND_TYPE_SEL;
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typedef enum {
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NAND_ERASE_UNCOND, ///< unconditional erase block
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NAND_ERASE_EMPTY, ///< erase block if this block is empty
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NAND_ERASE_LOGICALNUM ///< erase block if this block is selected logic block number
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} NAND_ERASE_CONDITION;
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/**
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SPI Flash Wide Bus Capability
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*/
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typedef enum {
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SPI_FLASH_BUSWIDTH_NORMAL = 0, //< Normal 1bit full duplex flash
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SPI_FLASH_BUSWIDTH_DUAL = 0x01, //< Support dual read (0x3B)
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SPI_FLASH_BUSWIDTH_QUAD_TYPE1 = 0x10, //< Support quad read (0xEB)
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//< But QE (Quad Enable) bit is in Status Register[bit 6]
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//< and 0xEB command requires 4 dummy clocks
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SPI_FLASH_BUSWIDTH_QUAD_TYPE2 = 0x20, //< Support quad read (0xEB)
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//< But QE (Quad Enable) bit is in Status Register[bit 9]
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//< and and 0xEB command requires 4 dummy clocks
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SPI_FLASH_BUSWIDTH_QUAD_TYPE3 = 0x40, //< Support quad read (0xEB)
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//< But not require QE (Quad Enable) bit and 0xEB command requires 8 dummy clocks
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SPI_FLASH_BUSWIDTH_QUAD_TYPE4 = 0x80, //< Support quad read, QE(Quad Enable) bit is in Status Register[bit 9] and 0xEB command requires 4 dummy clocks.
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//< But QE should be modified by 0x31 command
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SPI_FLASH_BUSWIDTH_QUAD_TYPE1_CMD31 = 0x100, //< Write status 0x31 command
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//< But QE should be modified by 0x31 command
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SPI_FLASH_BUSWIDTH_QUAD_TYPE5 = 0x200, //< Support quad read (0xEB)
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//< But QE should be modified by 0x31 command
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SPI_FLASH_BUSWIDTH_QUAD_DUMMY_6CYCLES = 0x400, //< Require 6 dummy cycles in quad DTR mode
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SPI_FLASH_BUSWIDTH_QUAD_DUMMY_10CYCLES = 0x800, //< Require 10 dummy cycles in quad DTR mode
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SPI_FLASH_BUSWIDTH_SINGLG_DUMMY_4CYCLES = 0x1000, //< Require 4 dummy cycles in single DTR mode
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SPI_FLASH_BUSWIDTH_SINGLG_DUMMY_8CYCLES = 0x2000, //< Require 8 dummy cycles in single DTR mode
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ENUM_DUMMY4WORD(SPI_FLASH_BUSWIDTH)
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} SPI_FLASH_BUSWIDTH;
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/**
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SPI flash identification structure
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@note For spiflash_open()
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*/
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typedef struct {
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UINT32 uiMfgID; //< manufacture ID
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UINT32 uiMemType; //< memory type
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UINT32 uiMemCapacity; //< memory capacity
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UINT32 uiTotalSize; //< total size (unit: byte)
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UINT32 uiSectorSize; //< sector size (unit: byte)
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UINT32 uiBlockSize; //< block size (unit: byte)
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UINT32 uiSectorCnt; //< sectr count (unit: sector)
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BOOL bSupportEWSR; //< support EWSR command
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BOOL bSupportAAI; //< support AAI command
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BOOL bSupportSecErase; //< support SECTOR_ERASE command (0x20)
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UINT32 uiChipEraseTime; //< CHIP erase time (unit: ms)
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UINT32 uiBlockEraseTime; //< Block erase time (unit: ms)
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UINT32 uiSectorEraseTime; //< Sector erase time (unit: ms)
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UINT32 uiPageProgramTime; //< page program time (unit: ms)
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SPI_FLASH_BUSWIDTH flashWidth; //< Wide bus (dual/quad) supported by this flash
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} SPI_FLASH_INFO, *PSPI_FLASH_INFO;
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/**
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SPI flash operation interface
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*/
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typedef struct {
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ER(*open)(void); //< open
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ER(*close)(void); //< close
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ER(*readID)(UINT8 *, UINT32); //< Read JEDEC ID from SPI nand
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//< Context are :
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//< - @b UINT8 * : Buffer to pass ID
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//< - @b UINT32 : buffer size (i.e. need to read how many bytes)
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ER(*eraseBlock)(UINT32); //< erase block
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//< Context are :
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//< - @b UINT32 : row address. Should be block alignment
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ER(*programPage)(UINT32, UINT32, UINT8 *, UINT32, UINT8 *, UINT32); // page program
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//< Context are:
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//< - @b UINT32: row address
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//< - @b UINT32: column address (valid range: 0 ~ 2111)
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//< - @b UINT8 * : buffer to be written to flash
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//< - @b UINT32 : buffer size
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//< - @b UINT8 * : buffer to write to spare aprea
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//< - @b UINT32 : spare area buffer size
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ER(*readPage)(UINT32, UINT32, UINT8 *, UINT32); // read page
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//< Context are:
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//< - @b UINT32: row address
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//< - @b UINT32: column address (valid range: 0 ~ 2111)
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//< - @b UINT8 * : buffer to be stored on DRAM
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//< - @b UINT32 : buffer size
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ER(*readMultiPage)(UINT32, UINT8 *, UINT32); // read whole block (skip spare area)
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//< Context are:
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//< - @b UINT32: row address
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//< - @b UINT8 * : buffer to be stored on DRAM
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//< - @b UINT32: page count
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ER(*setFreq)(UINT32); //< set operating frequency
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//< Context are:
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//< - @b UINT32 : frequency (unit: Hz)
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ER(*getStatus)(UINT32, UINT8 *);
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//< get status
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//< Context are:
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//< - @b UINT32 : SPI status set
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//< - @b UINT8 * : buffer to be stored on DRAM
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ER(*programBuffer)(UINT32, UINT8 *, UINT32); // page program into SPI NAND buffer
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//< Context are:
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//< - @b UINT32: column address (valid range: 0 ~ 2111)
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//< - @b UINT8 * : buffer to be written to flash
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//< - @b UINT32 : buffer size
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ER(*readBuffer)(UINT32, UINT8 *, UINT32); // read page from buffer
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//< Context are:
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//< - @b UINT32: column address (valid range: 0 ~ 2111)
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//< - @b UINT8 * : buffer to be stored on DRAM
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//< - @b UINT32 : buffer size
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ER(*setStatus)(UINT32, UINT8);
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//< set status frequency
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//< Context are:
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//< - @b UINT32 : SPI status set
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//< - @b UINT32 : SPI status to be write
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ER(*eraseNorSector)(UINT32); //< erase sector
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//< Context are :
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//< - @b UINT32 : address. Should be sector alignment (0x1000)
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ER(*norProgramPage)(UINT32, UINT32, UINT8 *);
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//< Nor flash page program(256 bytes)
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//< Context are :
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//< - @b UINT32 : address. Should be page alignment (256 bytes)
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//< - @b UINT32 : size Should be multiple of 256
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//< - @b UINT8 * : buffer to be stored on NAND
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ER(*norReadData)(UINT32, UINT32, UINT8 *);
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//< Nor flash read data(256 bytes)
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//< Context are :
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//< - @b UINT32 : address. Should be page alignment (256 bytes)
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//< - @b UINT32 : size Should be multiple of 256
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//< - @b UINT8 *: buffer to be stored on NAND
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} NAND_SPI_OBJ, *PNAND_SPI_OBJ;
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/**
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NAND host operation interface
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*/
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typedef struct {
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ER(*reset)(void);
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ER(*readID)(UINT8 *);
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ER(*eraseBlock)(UINT32);
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void (*nand_programSpare)(UINT16, UINT8, UINT8);
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ER(*nand_readOperation)(INT8 *, UINT32, UINT32);
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ER(*nand_writeOperation)(INT8 *, UINT32, UINT32);
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ER(*nand_condEraseBlock)(NAND_ERASE_CONDITION, UINT32, UINT32);
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ER(*nand_writeOperation_single)(INT8 *, UINT32, UINT32);
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ER(*nand_readPageSpareDataTotal)(UINT32 *, UINT32 *, UINT32 *, UINT32 *, UINT32);
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ER(*nand_readOperation_single)(INT8 *, UINT32, UINT32);
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ER(*nand_programBuffer)(UINT32, UINT8 *, UINT32);
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ER(*nand_readBuffer)(UINT32, UINT8 *, UINT32);
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ER(*nand_eraseSector)(UINT32);
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ER(*nand_readByBytes)(UINT32, UINT32, UINT8 *);
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ER(*nand_programSector)(UINT32, UINT32, UINT8 *);
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} NAND_HostCmdOps, *PNAND_HostCmdOps;
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/**
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SPI flash identification structure
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@note For SPIFLASH_IDENTIFY_CB
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*/
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typedef struct {
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UINT32 uiTotalSize; ///< total size (unit: byte)
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UINT32 uiSectorSize; ///< sector size (unit: byte)
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UINT32 uiBlockSize; ///< block size (unit: byte)
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UINT32 uiSectorCnt; ///< sectr count (unit: sector)
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BOOL bSupportEWSR; ///< support EWSR command
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BOOL bSupportAAI; ///< support AAI command
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BOOL bSupportSecErase; ///< support SECTOR_ERASE command (0x20)
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UINT32 uiChipEraseTime; ///< CHIP erase time (unit: ms)
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UINT32 uiBlockEraseTime; ///< Block erase time (unit: ms)
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UINT32 uiSectorEraseTime; ///< Sector erase timeout (unit: ms)
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UINT32 uiPageProgramTime; ///< page program timeout (unit: ms)
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SPI_FLASH_BUSWIDTH flashWidth; ///< Wide bus (dual/quad) supported by this flash
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} SPIFLASH_IDENTIFY, *PSPIFLASH_IDENTIFY;
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/**
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SPIFLASH identify callback
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Callback routine to be invoked after JEDEC ID is read from spi flash.
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Callback routine should check if read ID is supported.
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@note STRG_EXT_CMD_SPI_IDENTIFY_CB
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@param[in] first parameter (JEDEC) manufacturer ID read from spi flash
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@param[in] second parameter (JEDEC) type ID read from spi flash
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@param[in] third parameter (JEDEC) capacity ID read from spi flash
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@param[out] forth parameter flash identification returned to spi flash driver
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@return
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- @b TRUE: call back will handle identification of this flash. and PSPI_IDENTIFY will fill identifed information
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- @b FALSE: input ID is NOT supported/identified by call back
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*/
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typedef BOOL (*SPIFLASH_IDENTIFY_CB)(UINT32, UINT32, UINT32, PSPIFLASH_IDENTIFY);
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extern ER nand_emuReadPageSpareDataTotal(UINT32 *spare0, UINT32 *spare1, UINT32 *spare2, UINT32 *spare3, UINT32 pageAddress);
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extern ER nand_setFeature(NAND_FEATRUE Nand_Feature, UINT32 uiParameter);
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#if _NAND2_SUPPORT_
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extern PSTRG_TAB nand2_getStorageObject(void);
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extern ER nand2_writeSectors(INT8 *pcBuf, UINT32 ulSecNum, UINT32 ulSctCnt);
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extern ER nand2_readSectors(INT8 *pcBuf, UINT32 ulSecNum, UINT32 ulSctCnt);
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extern void nand2_setSize(UINT32 size);
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ER nand2_format(void);
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void nand2_FormatEraseNAND(void);
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#endif
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extern ER nand_setConfig(NAND_CONFIG_ID ConfigID, UINT32 uiConfig);
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extern INT32 nand_getConfig(NAND_CONFIG_ID ConfigID);
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extern void nand_dumpInfo(void);
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extern void nand_dumpAllData(UINT32 uiBuf, UINT32 uiSize);
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extern PSTORAGE_OBJ nand_getStorageObject(STRG_OBJ_ID strgObjID);
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extern void nand_init_fat_storage_object(void);
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extern void nand_eraseAllPartitionBlockMapping(BOOL bForceErMarked, BOOL bForceErDefected, BOOL force_erase_all);
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extern PNAND_SPI_OBJ nand_ctrl_spi_nor_getObject(void);
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extern ER nand_attach(void);
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extern void nand_detach(void);
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extern ER nand_identify(void);
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extern BOOL spiflash_isInfoReady(void);
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extern ER spiflash_getAttachFlashInfo(PSPI_FLASH_INFO *pFlashInfo);
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//@}
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#endif // _NAND_H
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