309 lines
6.9 KiB
C
Executable File
309 lines
6.9 KiB
C
Executable File
/**
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Header file for Interrupt module
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This file is the header file that define the API for Interrupt module.
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@file Interrupt.h
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@ingroup mIDrvSys_Interrupt
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@note Nothing.
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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*/
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#ifndef _INTERRUPT_H
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#define _INTERRUPT_H
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#include <kwrap/nvt_type.h>
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// Interrupt number <= 32
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//typedef UINT32 INT_PTN;
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// Interrupt number > 32
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typedef UINT64 INT_PTN;
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/**
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Interrupt module ID
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Interrupt module ID for int_getIRQId() and int_getDummyId().
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*/
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#define INT_GIC_SPI_START_ID 32
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typedef enum {
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INT_ID_TIMER = INT_GIC_SPI_START_ID, // 0
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INT_ID_SIE, // 1
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INT_ID_SIE2, // 2
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INT_ID_SIE3, // 3
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INT_ID_DRTC, // 4
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INT_ID_IPE, // 5
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INT_ID_IME, // 6
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INT_ID_DCE, // 7
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INT_ID_IFE, // 8
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INT_ID_IFE2, // 9
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INT_ID_DIS, //10
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INT_ID_CNN, //11
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INT_ID_SDP, //12
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INT_ID_RHE, //13
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INT_ID_DRE, //14
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INT_ID_DAI, //15
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INT_ID_H26X, //16
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INT_ID_JPEG, //17
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INT_ID_GRAPHIC, //18
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INT_ID_GRAPHIC2, //19
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INT_ID_RSA, //20
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INT_ID_ISE, //21
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INT_ID_TGE, //22
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INT_ID_TSE, //23
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INT_ID_GPIO, //24
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INT_ID_REMOTE, //25
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INT_ID_PWM, //26
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INT_ID_USB, //27
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INT_ID_HASH, //28
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INT_ID_NAND, //29
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INT_ID_SDIO, //30
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INT_ID_SDIO2, //31
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INT_ID_SDIO3, //32
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INT_ID_DMA, //33
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INT_ID_ETHERNET, //34
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INT_ID_SPI, //35
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INT_ID_SPI2, //36
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INT_ID_SPI3, //37
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INT_ID_CRYPTO, //38
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INT_ID_ETH_REV_MII, //39
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INT_ID_SIF, //40
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INT_ID_I2C, //41
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INT_ID_I2C2, //42
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INT_ID_UART, //43
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INT_ID_UART2, //44
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INT_ID_UART3, //45
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INT_ID_MDBC, //46
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INT_ID_ADC, //47
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INT_ID_IDE, //48
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INT_ID_CNN2, //49
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INT_ID_DSI, //50
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INT_ID_DMA2, //51
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INT_ID_AFFINE, //52
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INT_ID_IVE, //53 (o)
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INT_ID_LVDS, //54
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INT_ID_LVDS2, //55
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INT_ID_RTC, //56
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INT_ID_WDT, //57
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INT_ID_CG, //58
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INT_ID_UVCP, //59
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INT_ID_I2C3, //60
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INT_ID_SIE5, //61 @ NT98528
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INT_ID_VPE, //62 @ NT98528
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INT_ID_UART4, //63 @ NT98528
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INT_ID_UART5, //64 @ NT98528
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INT_ID_UART6, //65 @ NT98528
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INT_ID_SPI4, //66 @ NT98528
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INT_ID_SPI5, //67 @ NT98528
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INT_ID_I2C4, //68 @ NT98528
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INT_ID_I2C5, //69 @ NT98528
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INT_ID_TIMER2, //70 @ NT98528
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INT_ID_GPIO2, //71 @ NT98528
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INT_ID_SIF2, //72 @ NT98528
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INT_ID_PWM2, //73 @ NT98528
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INT_ID_SDE, //74 @ NT98528
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INT_ID_DUMMY_DGPIO,
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INT_ID_CNT,
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INT_ID_MAX = INT_ID_CNT - INT_GIC_SPI_START_ID, //94
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INT_ID_WFI = 229,
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INT_ID_SIE4,
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INT_ID_GIC_TOTAL = 256,
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ENUM_DUMMY4WORD(INT_ID)
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} INT_ID;
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typedef union {
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INT_PTN reg[4];
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struct {
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UINT32 bInt_ID_PPI:32;
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//INT0
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UINT32 bInt_ID_TIMER: 1;
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UINT32 bInt_ID_SIE: 1;
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UINT32 bInt_ID_SIE2: 1;
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UINT32 bInt_ID_SIE3: 1;
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UINT32 bInt_ID_DRTC: 1;
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UINT32 bInt_ID_IPE: 1;
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UINT32 bInt_ID_IME: 1;
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UINT32 bInt_ID_DCE: 1;
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UINT32 bInt_ID_IFE: 1;
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UINT32 bInt_ID_IFE2: 1;
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UINT32 bInt_ID_DIS: 1;
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UINT32 bInt_ID_FDE: 1;
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// UINT32 bInt_ID_RDE:1;
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UINT32 bInt_ID_Ethernet_LPI: 1;
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UINT32 bInt_ID_RHE: 1;
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UINT32 bInt_ID_DRE: 1;
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UINT32 bInt_ID_DAI: 1;
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//INT16
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UINT32 bInt_ID_H264: 1;
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UINT32 bInt_ID_JPEG: 1;
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UINT32 bInt_ID_GRAPHIC: 1;
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UINT32 bInt_ID_GRAPHIC2: 1;
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UINT32 bInt_ID_RSA: 1;
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UINT32 bInt_ID_ISE: 1;
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UINT32 bInt_ID_TGE: 1;
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UINT32 bInt_ID_TSMUX: 1;
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UINT32 bInt_ID_GPIO: 1;
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UINT32 bInt_ID_REMOTE: 1;
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UINT32 bInt_ID_PWM: 1;
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UINT32 bInt_ID_USB: 1;
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UINT32 bInt_ID_HASH: 1;
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UINT32 bInt_ID_NAND: 1;
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UINT32 bInt_ID_SDIO: 1;
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UINT32 bInt_ID_SDIO2: 1;
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//INT32
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UINT32 bInt_ID_SDIO3: 1;
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UINT32 bInt_ID_DMA: 1;
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UINT32 bInt_ID_ETHERNET: 1;
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UINT32 bInt_ID_SPI: 1;
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UINT32 bInt_ID_SPI2: 1;
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UINT32 bInt_ID_SPI3: 1;
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UINT32 bInt_ID_SCE: 1;
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UINT32 bInt_ID_Ehternet_RevMII: 1;
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// UINT32 bInt_ID_SPI5:1;
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UINT32 bInt_ID_SIF: 1;
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UINT32 bInt_ID_I2C: 1;
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UINT32 bInt_ID_I2C2: 1;
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UINT32 bInt_ID_UART: 1;
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UINT32 bInt_ID_UART2: 1;
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UINT32 bInt_ID_UART3: 1;
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UINT32 bInt_ID_MDBC: 1;
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UINT32 bInt_ID_ADC: 1;
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//INT48
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UINT32 bInt_ID_IDE: 1;
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UINT32 bInt_ID_CNN2: 1;
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UINT32 bInt_ID_DSI: 1;
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UINT32 bInt_ID_DMA2: 1;
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//INT52
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UINT32 bInt_ID_AFFINE: 1;
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UINT32 bInt_ID_IVE: 1;
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UINT32 bInt_ID_LVDS: 1; // LVDS& HiSPI& CSI
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UINT32 bInt_ID_LVDS2: 1; //LVDS2&HiSPI2&CSI2
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//INT56
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UINT32 bInt_ID_RTC: 1;
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UINT32 bInt_ID_WDT: 1;
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UINT32 bInt_ID_CG: 1;
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UINT32 bInt_ID_SIE4: 1; //@NT98528
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//INT60
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UINT32 bInt_ID_I2C3: 1;
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UINT32 bInt_ID_SIE5: 1; //@NT98528
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UINT32 bInt_ID_VPE: 1; //@NT98528
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UINT32 bInt_ID_UART4: 1; //@NT98528
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//INT64
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UINT32 bInt_ID_UART5: 1; //@NT98528
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UINT32 bInt_ID_UART6: 1; //@NT98528
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UINT32 bInt_ID_SPI4: 1; //@NT98528
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UINT32 bInt_ID_SPI5: 1; //@NT98528
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//INT68
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UINT32 bInt_ID_I2C4: 1;
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UINT32 bInt_ID_I2C5: 1;
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UINT32 bInt_ID_TIMER2: 1;
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UINT32 bInt_ID_GPIO2: 1;
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//INT72
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UINT32 bInt_ID_SIF2: 1;
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UINT32 bInt_ID_PWM2: 1;
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UINT32 bInt_ID_SDE: 1;
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UINT32 bInt_ID_RSV: 1;
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//INT76 => 4
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UINT32 bReserved76: 4;
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//INT80=> 4
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UINT32 bReserved80: 4;
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//INT84=> 4
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UINT32 bReserved84: 4;
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//INT88=> 4
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UINT32 bReserved88: 4;
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//INT92=> 4
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UINT32 bReserved92: 4;
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} Bit;
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} INT_GIC_ID_ENABLE, *PINT_GIC_ID_ENABLE;
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typedef struct {
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INT_GIC_ID_ENABLE int_id_enable;
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} INT_INTC_ENABLE, *PINT_INTC_ENABLE;
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#define IRQF_TRIGGER_NONE 0x00000000
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#define IRQF_TRIGGER_RISING 0x00000001
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#define IRQF_TRIGGER_FALLING 0x00000002
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#define IRQF_TRIGGER_HIGH 0x00000004
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#define IRQF_TRIGGER_LOW 0x00000008
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typedef enum {
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IRQF_BH_PRI_LOW = 0x00000100,
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IRQF_BH_PRI_MIDDLE = 0x00000200,
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IRQF_BH_PRI_HIGH = 0x00000400,
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IRQF_BH_PRI_DEFAULT = IRQF_BH_PRI_MIDDLE,
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ENUM_DUMMY4WORD(IRQF_BH)
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}IRQF_BH;
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enum irqreturn {
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IRQ_NONE = (0 << 0),
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IRQ_HANDLED = (1 << 0),
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IRQ_WAKE_THREAD = (1 << 1),
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};
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typedef enum irqreturn irqreturn_t;
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typedef irqreturn_t (* irq_handler_t)(int irq, void *dev);
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typedef irqreturn_t (* irq_bh_handler_t)(int irq, unsigned long event, void *data);
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extern void irq_init(void);
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extern int request_irq(unsigned int irq, irq_handler_t handler, unsigned long flags, const char *name, void *dev);
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extern void free_irq(unsigned int irq, void *dev);
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extern int request_irq_bh(unsigned int irq, irq_bh_handler_t bh_handler, IRQF_BH flags);
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extern void free_irq_bh(unsigned int irq, void *dev);
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extern int kick_bh(unsigned int irq, unsigned long event, void *data);
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extern void int_enable_multi(INT_INTC_ENABLE gic_int_en);
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extern void int_disable_multi(INT_INTC_ENABLE gic_int_en);
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extern void int_get_gic_enable(PINT_INTC_ENABLE gic_int_en);
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extern void int_gic_set_target(unsigned int number, unsigned int target);
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//@}
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#endif
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