335 lines
11 KiB
C
Executable File
335 lines
11 KiB
C
Executable File
/**
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@file pwm.h
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@ingroup mIDrvIO_PWM
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@brief Header file for PWM module
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This file is the header file that define the API for PWM module
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Copyright Novatek Microelectronics Corp. 2012. All rights reserved.
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*/
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#ifndef __ARCH_PWM_H
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#define __ARCH_PWM_H
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/**
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@addtogroup mIDrvIO_PWM
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*/
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//@{
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/**
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PWM type (PWM or Micro step)
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*/
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typedef enum
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{
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PWM_TYPE_PWM = 0x0, ///< PWM
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PWM_TYPE_MICROSTEP, ///< Micro step
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// ENUM_DUMMY4WORD(PWM_TYPE)
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} PWM_TYPE;
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/**
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PWM micro step direction
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Micro step direction configuration
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@note for pwm_mstepConfig() pwm_mstepConfigSet()
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*/
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typedef enum
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{
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MS_DIR_INCREASE = 0x0, ///< CounterClockwise
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MS_DIR_DECREASE, ///< Clockwise
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MS_DIR_CNT,
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// ENUM_DUMMY4WORD(PWM_MS_DIR)
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} PWM_MS_DIR;
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/**
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PWM micro step phase type (1-2 or 2-2 phase)
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@note for pwm_mstepConfig() pwm_mstepConfigSet()
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*/
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typedef enum
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{
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PWM_MS_1_2_PHASE_TYPE = 0x0, ///< 1 unit each operation
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PWM_MS_2_2_PHASE_TYPE, ///< 2 unit each operation
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PWM_MS_PHASE_TYPE_CNT,
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// ENUM_DUMMY4WORD(PWM_MS_PHASE_TYPE)
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} PWM_MS_PHASE_TYPE;
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/**
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PWM Micro step step per phase
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PWM Micro step step per phase configuration
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@note for pwm_mstepConfig() pwm_mstepConfigSet()
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*/
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typedef enum
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{
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TOTAL_08_STEP_PER_PHASE = 8, ///< 8 steps each phase
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TOTAL_16_STEP_PER_PHASE = 16, ///< 16 steps each phase
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TOTAL_32_STEP_PER_PHASE = 32, ///< 32 steps each phase
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TOTAL_64_STEP_PER_PHASE = 64, ///< 64 steps each phase
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// ENUM_DUMMY4WORD(PWM_MS_STEP_PER_PHASE)
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} PWM_MS_STEP_PER_PHASE;
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/**
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PWM Micro step channel level
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PWM Micro step channel level configuation
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*/
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typedef enum
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{
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PWM_MS_CHANNEL_LEVEL_LOW = 0x0, ///< PWM MS channel level low
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PWM_MS_CHANNEL_LEVEL_HIGH, ///< PWM MS channel level high
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// ENUM_DUMMY4WORD(PWM_MS_CHANNEL_LEVEL)
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} PWM_MS_CHANNEL_LEVEL;
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/**
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PWM Micro step channel set
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PWM Micro step channel set definition
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@note for pwm_openSet, pwm_closeSet, pwm_waitSet(), pwm_configClockDivSet(), pwm_mstepConfigSet(),\n
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pwm_pwmEnableSet(), pwm_pwmDisableSet(), pwm_mstepEnableSet(), pwm_mstepDisableSet()
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*/
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typedef enum
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{
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PWM_MS_SET_0 = 0x0, ///< PWM MS channel set 0, including PWM0-3
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PWM_MS_SET_1, ///< PWM MS channel set 1, including PWM4-7
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PWM_MS_SET_2, ///< PWM MS channel set 2, including PWM8-11
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PWM_MS_SET_3, ///< PWM MS channel set 3, including PWM12-15
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PWM_MS_SET_TOTAL,
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// ENUM_DUMMY4WORD(PWM_MS_CHANNEL_SET)
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} PWM_MS_CHANNEL_SET;
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/**
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Micro step target count set(s)
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@note for pwm_mstepConfigTargetCountEnable()
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*/
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typedef enum
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{
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PWM_00_03_TGT_CNT = 0x0, ///< PWM0~PWM3 target count
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PWM_04_07_TGT_CNT, ///< PWM4~PWM7 target count
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PWM_08_11_TGT_CNT, ///< PWM8~PWM11 target count
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PWM_TGT_CNT_NUM,
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// ENUM_DUMMY4WORD(PWM_TGT_COUNT)
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} PWM_TGT_COUNT;
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/**
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PWM clock divid
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@note for pwm_pwmConfigClockDiv()
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*/
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typedef enum
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{
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PWM0_3_CLKDIV = 0x0, ///< PWM0~PWM3 clock divid
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PWM4_7_CLKDIV, ///< PWM4~PWM7 clock divid
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PWM8_11_CLKDIV, ///< PWM8~PWM11 clock divid
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PWM12_CLKDIV = 12, ///< PWM12 clock divid
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PWM13_CLKDIV, ///< PWM13 clock divid
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PWM14_CLKDIV, ///< PWM14 clock divid
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PWM15_CLKDIV, ///< PWM15 clock divid
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PWM16_CLKDIV, ///< PWM16 clock divid
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PWM17_CLKDIV, ///< PWM17 clock divid
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PWM18_CLKDIV, ///< PWM18 clock divid
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PWM19_CLKDIV, ///< PWM19 clock divid
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// ENUM_DUMMY4WORD(PWM_CLOCK_DIV)
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} PWM_CLOCK_DIV;
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/**
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PWM status selection
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*/
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typedef enum
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{
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PWM_MS_STS, ///< PWM micro stepping status
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PWM_STS, ///< PWM status
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PWM_CLKLOAD_STS, ///< PWM clock load status
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PWM_TGTCNT_STS, ///< PWM target count status
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// ENUM_DUMMY4WORD(PWM_STS_SELECTION)
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} PWM_STS_SELECTION;
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/**
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PWM configuration identifier
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@note For pwm_setConfig()
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*/
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typedef enum
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{
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PWM_CONFIG_ID_AUTOPINMUX, ///< Context can be one of the following:
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///< - @b TRUE : disable pinmux when pwm driver close
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///< - @b FALSE : not disable pinmux when pwm driver close
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// ENUM_DUMMY4WORD(PWM_CONFIG_ID)
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} PWM_CONFIG_ID;
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/**
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PWM configuration structure
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@note for pwm_set()
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*/
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typedef struct
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{
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u32 uiPrd; ///< Base period, how many PWM clock per period, 2 ~ 255
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///< @note uiRise <= uiFall <= uiPrd
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u32 uiRise; ///< Rising at which clock
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///< @note uiRise <= uiFall <= uiPrd
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u32 uiFall; ///< Falling at which clock
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///< @note uiRise <= uiFall <= uiPrd
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u32 uiOnCycle; ///< Output cycle, 0 ~ 65535
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///< - @b PWM_FREE_RUN: Free Run
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///< - @b Others: How many cycles (PWM will stop after output the cycle counts)
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u32 uiInv; ///< Invert PWM output signal or not
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///< - @b PWM_SIGNAL_NORMAL: Don't invert PWM output signal
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///< - @b PWM_SIGNAL_INVERT: Invert PWM output signal
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} PWM_CFG, *PPWM_CFG;
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/**
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MSTP configuration structure
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@note for pwm_mstepConfig()
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*/
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typedef struct
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{
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u32 uiPh; ///< Micro step starting phase, phase 0 ~ 7
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u32 uiDir; ///< Micro step moving direction ,
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///< - @b MS_DIR_INCREASE
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///< - @b MS_DIR_DECREASE
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u32 uiOnCycle; ///< Number of phase for Micro step mode
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u32 uiStepPerPhase; ///< Step per phase
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///< - @b TOTAL_08_STEP_PER_PHASE (8 steps each phase)
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///< - @b TOTAL_16_STEP_PER_PHASE (16 steps each phase)
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///< - @b TOTAL_32_STEP_PER_PHASE (32 steps each phase)
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///< - @b TOTAL_64_STEP_PER_PHASE (64 steps each phase)
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u32 uiPhaseType; ///< 1-2 or 2-2 phase
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///< - @b PWM_MS_1_2_PHASE_TYPE (1 unit each operation)
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///< - @b PWM_MS_2_2_PHASE_TYPE (2 unit each operation)
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BOOL uiThresholdEn; ///< Enable threshold filter(always set as FALSE), TRUE for test only
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BOOL uiThreshold; ///< Max 0x63
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} MSTP_CFG, *PMSTP_CFG;
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/**
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Micro step channels (within a set) phase configuration
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@note for pwm_mstepConfigSet()
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*/
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typedef struct
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{
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u32 uiCH0_Phase; ///< Specific MS set channel 0 start phase
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u32 uiCH1_Phase; ///< Specific MS set channel 1 start phase
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u32 uiCH2_Phase; ///< Specific MS set channel 2 start phase
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u32 uiCH3_Phase; ///< Specific MS set channel 3 start phase
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} MS_CH_PHASE_CFG, *PMS_CH_PHASE_CFG;
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/**
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Micro step channels (within a set) level configuration
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@note for PWM_MS_CHANNEL_LEVEL_LOW or PWM_MS_CHANNEL_LEVEL_HIGH,
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*/
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typedef struct
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{
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u32 uiCH0_Level; ///< Specific MS channel 0 level
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u32 uiCH1_Level; ///< Specific MS channel 1 level
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u32 uiCH2_Level; ///< Specific MS channel 2 level
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u32 uiCH3_Level; ///< Specific MS channel 3 level
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} MS_CH_LEVEL_CFG, *PMS_CH_LEVEL_CFG;
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/**
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MSTP configuration structure
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@note for pwm_mstepConfigSet()
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*/
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typedef struct
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{
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u32 uiDir; ///< Micro step moving direction ,
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///< - @b MS_DIR_INCREASE
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///< - @b MS_DIR_DECREASE
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u32 uiOnCycle; ///< Number of phase for Micro step mode
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u32 uiStepPerPhase; ///< Step per phase
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///< - @b TOTAL_08_STEP_PER_PHASE (8 steps each phase)
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///< - @b TOTAL_16_STEP_PER_PHASE (16 steps each phase)
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///< - @b TOTAL_32_STEP_PER_PHASE (32 steps each phase)
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///< - @b TOTAL_64_STEP_PER_PHASE (64 steps each phase)
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u32 uiPhaseType; ///< 1-2 or 2-2 phase
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///< - @b PWM_MS_1_2_PHASE_TYPE (1 unit each operation)
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///< - @b PWM_MS_2_2_PHASE_TYPE (2 unit each operation)
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BOOL uiThresholdEn; ///< Enable threshold filter
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BOOL uiThreshold; ///< Max 0x63
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} MSCOMMON_CFG, *PMSCOMMON_CFG;
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/**
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@name PWM ID
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PWM ID for PWM driver API
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@note for pwm_open(), pwm_set(), pwm_setCCNT(), pwm_setCCNTToutEN(), pwm_wait(), pwm_stop(), pwm_en(), pwm_reload(),\n
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pwm_ms_set(), pwm_ms_stop(), pwm_ms_en(), pwm_getCycleNumber(), pwm_ccntGetCurrentVal(), pwm_ccntGetCurrentVal(),\n
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pwm_ccntEnable()
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*/
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//@{
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#define PWMID_0 0x00000001 ///< PWM ID 0
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#define PWMID_1 0x00000002 ///< PWM ID 1
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#define PWMID_2 0x00000004 ///< PWM ID 2
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#define PWMID_3 0x00000008 ///< PWM ID 3
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#define PWMID_4 0x00000010 ///< PWM ID 4
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#define PWMID_5 0x00000020 ///< PWM ID 5
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#define PWMID_6 0x00000040 ///< PWM ID 6
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#define PWMID_7 0x00000080 ///< PWM ID 7
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#define PWMID_8 0x00000100 ///< PWM ID 8
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#define PWMID_9 0x00000200 ///< PWM ID 9
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#define PWMID_10 0x00000400 ///< PWM ID 10
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#define PWMID_11 0x00000800 ///< PWM ID 11
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#define PWMID_12 0x00001000 ///< PWM ID 12
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#define PWMID_13 0x00002000 ///< PWM ID 13
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#define PWMID_14 0x00004000 ///< PWM ID 14
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#define PWMID_15 0x00008000 ///< PWM ID 15
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#define PWMID_16 0x00010000 ///< PWM ID 16
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#define PWMID_17 0x00020000 ///< PWM ID 17
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#define PWMID_18 0x00040000 ///< PWM ID 18
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#define PWMID_19 0x00080000 ///< PWM ID 19
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//@}
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// PWM Driver API
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extern int pwm_open(u32 uiPWMId);
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extern int pwm_openSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern u32 pwm_pwmGetCycleNumber(u32 uiPWMId);
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extern int pwm_close(u32 uiPWMId, BOOL bWaitAutoDisableDone);
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extern int pwm_closeSet(PWM_MS_CHANNEL_SET uiMSSet, BOOL bWaitAutoDisableDone);
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extern int pwm_wait(u32 uiPWMId, PWM_TYPE uiPwmType);
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extern int pwm_waitSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern int pwm_pwmReload(u32 uiPWMId);
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extern int pwm_pwmEnable(u32 uiPWMId);
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extern int pwm_pwmDisable(u32 uiPWMId);
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extern int pwm_pwmEnableSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern int pwm_pwmDisableSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern int pwm_pwmConfig(u32 uiPWMId, PPWM_CFG pPWMCfg);
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extern int pwm_pwmConfigClockDiv(PWM_CLOCK_DIV uiClkSrc, u32 uiDiv);
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extern int pwm_pwmReloadConfig(u32 uiPWMId, u32 iRise, u32 iFall, u32 iBasePeriod);
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extern int pwm_mstepEnable(u32 uiPWMId);
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extern int pwm_mstepDisable(u32 uiPWMId, BOOL bWait);
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extern int pwm_mstepEnableSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern int pwm_mstepDisableSet(PWM_MS_CHANNEL_SET uiMSSet);
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extern int pwm_mstepClockDivReload(PWM_CLOCK_DIV uiPWMClkDiv, BOOL bWaitDone);
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extern int pwm_mstepConfig(u32 uiPWMId, PMSTP_CFG pMSTPCfg);
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extern int pwm_mstepTargetCountWaitDone(PWM_TGT_COUNT uiTargetCnt);
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extern int pwm_mstepClkDivWaitLoadDone(PWM_CLOCK_DIV uiPWMClkDivSrc);
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extern int pwm_mstepConfigClockDiv(PWM_MS_CHANNEL_SET uiMSSet, u32 uiDiv);
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extern int pwm_mstepConfigTargetCountEnable(PWM_TGT_COUNT uiTargetCntSet, u32 uiTargetCnt, BOOL bEnableTargetCnt);
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extern int pwm_mstepConfigSet(PWM_MS_CHANNEL_SET uiMSSet, PMS_CH_PHASE_CFG pMSSetChPhCfg, PMSCOMMON_CFG pMSCommonCfg);
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extern void pwm_setup_start(u32 pwm_id, u32 duty_cycle, u32 signal_inv);
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extern void pwm_reload(u32 pwm_id, u32 duty_cycle, u32 signal_inv);
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//@}
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#endif /* __ARCH_PWM_H */
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