393 lines
9.8 KiB
C
Executable File
393 lines
9.8 KiB
C
Executable File
/**
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NVT evb board file
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To handle na51xxx HW init.
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@file na51xxx_hw_init.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2019. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/mach-types.h>
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#include <asm/nvt-common/nvt_common.h>
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#include <asm/nvt-common/rcw_macro.h>
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#include <asm/arch/IOAddress.h>
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#include <asm/arch/efuse_protected.h>
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#ifdef CONFIG_NVT_IVOT_DDR_RANGE_SCAN_SUPPORT
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#include <asm/arch/raw_scanMP.h>
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#include <asm/arch/hardware.h>
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#endif
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#include <linux/libfdt.h>
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#define WDT_REG_ADDR(ofs) (IOADDR_WDT_REG_BASE+(ofs))
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#define WDT_GETREG(ofs) readl(WDT_REG_ADDR(ofs))
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#define WDT_SETREG(ofs,value) writel(value, WDT_REG_ADDR(ofs))
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#define CG_REG_ADDR(ofs) (IOADDR_CG_REG_BASE+(ofs))
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#define CG_GETREG(ofs) readl(CG_REG_ADDR(ofs))
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#define CG_SETREG(ofs,value) writel(value, CG_REG_ADDR(ofs))
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#define PAD_REG_ADDR(ofs) (IOADDR_PAD_REG_BASE+(ofs))
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#define PAD_GETREG(ofs) readl(PAD_REG_ADDR(ofs))
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#define PAD_SETREG(ofs,value) writel(value, PAD_REG_ADDR(ofs))
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#define TOP_REG_ADDR(ofs) (IOADDR_TOP_REG_BASE+(ofs))
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#define TOP_GETREG(ofs) readl(TOP_REG_ADDR(ofs))
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#define TOP_SETREG(ofs,value) writel(value, TOP_REG_ADDR(ofs))
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#define CG_PLL_ENABLE_OFS 0x0
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#define CG_ENABLE_OFS 0x7C
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#define CG_RESET_OFS 0x9C
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#define CG_PLL4_DIV0_OFS 0x1318
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#define CG_PLL4_DIV1_OFS 0x131C
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#define CG_PLL4_DIV2_OFS 0x1320
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#define WDT_POS (1 << 4)
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#define WDT_RST (1 << 12)
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#define WDT_CTRL_OFS 0x0
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#if defined(CONFIG_SD_CARD1_POWER_PIN) || defined(CONFIG_SD_CARD2_POWER_PIN) || defined(ETH_PHY_HW_RESET)
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static void gpio_set_output(u32 pin)
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{
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u32 reg_data;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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reg_data = readl((unsigned long)(IOADDR_GPIO_REG_BASE + 0x20 + ofs));
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reg_data |= (1 << pin); //output
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writel(reg_data, (unsigned long)(IOADDR_GPIO_REG_BASE + 0x20 + ofs));
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}
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static void gpio_set_pin(u32 pin)
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{
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u32 tmp;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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tmp = (1 << pin);
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writel(tmp, (unsigned long)(IOADDR_GPIO_REG_BASE + 0x40 + ofs));
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}
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static void gpio_clear_pin(u32 pin)
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{
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u32 tmp;
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u32 ofs = (pin >> 5) << 2;
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pin &= (32 - 1);
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tmp = (1 << pin);
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writel(tmp, (unsigned long)(IOADDR_GPIO_REG_BASE + 0x60 + ofs));
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}
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#endif
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void nvt_ivot_reset_cpu(void)
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{
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u32 reg_value;
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reg_value = CG_GETREG(CG_RESET_OFS);
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CG_SETREG(CG_RESET_OFS, reg_value | WDT_RST);
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reg_value = CG_GETREG(CG_ENABLE_OFS);
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CG_SETREG(CG_ENABLE_OFS, reg_value | WDT_POS);
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WDT_SETREG(WDT_CTRL_OFS, 0x5A960112);
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udelay(80);
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WDT_SETREG(WDT_CTRL_OFS, 0x5A960113);
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}
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static void ethernet_init(void)
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{
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#if 0
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ulong fdt_addr = nvt_readl((ulong)nvt_shminfo_boot_fdt_addr);
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int nodeoffset, len;
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u32 *cell = NULL;
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char path[20] = {0};
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u32 sensor_cfg = 0x0, eth_cfg = 0x0, reg_val = 0x0;
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sprintf(path,"/top@%x/sensor",IOADDR_TOP_REG_BASE);
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nodeoffset = fdt_path_offset((const void*)fdt_addr, path);
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if (nodeoffset < 0) {
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printf("%s(%d) nodeoffset < 0\n",__func__, __LINE__);
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return ;
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}
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cell = (u32*)fdt_getprop((const void*)fdt_addr, nodeoffset, "pinmux", &len);
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if (len == 0) {
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printf("%s(%d) len = 0\n",__func__, __LINE__);
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return ;
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}
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sensor_cfg = __be32_to_cpu(cell[0]);
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debug("%s(%d) sensor_cfg = 0x%x\n", __func__, __LINE__, sensor_cfg);
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sprintf(path,"/eth@%x",IOADDR_ETH_REG_BASE);
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nodeoffset = fdt_path_offset((const void*)fdt_addr, path);
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if (nodeoffset < 0) {
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printf("%s(%d) nodeoffset < 0\n", __func__, __LINE__);
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return ;
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}
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cell = (u32*)fdt_getprop((const void*)fdt_addr, nodeoffset, "sp-clk", &len);
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if (len == 0) {
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printf("%s(%d) len = 0\n", __func__, __LINE__);
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return ;
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}
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eth_cfg = __be32_to_cpu(cell[0]);
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debug("%s(%d) eth_cfg = 0x%x\n", __func__, __LINE__, eth_cfg);
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if ((sensor_cfg & 0x20000) || (eth_cfg == 1)) {
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/* Disable PLL4 */
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reg_val = CG_GETREG(CG_PLL_ENABLE_OFS);
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reg_val &= ~(0x1 << 4);
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CG_SETREG(CG_PLL_ENABLE_OFS, reg_val);
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CG_SETREG(CG_PLL4_DIV0_OFS, 0x0);
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CG_SETREG(CG_PLL4_DIV1_OFS, 0x0);
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CG_SETREG(CG_PLL4_DIV2_OFS, 0x32);
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/* spclk_sel: pll4 */
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reg_val = CG_GETREG(0x24);
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reg_val &= ~0x4300;
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reg_val |= (0x1 << 8);
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CG_SETREG(0x24, reg_val);
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reg_val = CG_GETREG(0x3C);
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reg_val &= ~0xFF000000;
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reg_val |= (0xB << 24);
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CG_SETREG(0x3C, reg_val);
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/* Enable PLL4 */
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reg_val = CG_GETREG(CG_PLL_ENABLE_OFS);
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reg_val |= (0x1 << 4);
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CG_SETREG(CG_PLL_ENABLE_OFS, reg_val);
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/* Enable SP_CLK */
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reg_val = CG_GETREG(0x70);
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reg_val |= (0x1 << 12);
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CG_SETREG(0x70, reg_val);
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/* Pinmux SP_CLK1 */
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reg_val = TOP_GETREG(0xC);
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reg_val &= ~(0x3 << 18);
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reg_val |= (0x1 << 18);
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TOP_SETREG(0xC, reg_val);
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/* Pinmux P_GPIO17 */
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reg_val = TOP_GETREG(0xA8);
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reg_val &= ~(0x1 << 17);
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TOP_SETREG(0xA8, reg_val);
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}
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#endif
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#ifdef ETH_PHY_HW_RESET
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gpio_set_output(NVT_PHY_RST_PIN);
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gpio_clear_pin(NVT_PHY_RST_PIN);
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mdelay(20);
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gpio_set_pin(NVT_PHY_RST_PIN);
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mdelay(50);
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#endif
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}
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static void usbphy_init(void)
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{
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#if 0
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if (TOP_GETREG(0xF0) == 0x50210000) {
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//printf("********************%s(%d) Add USB528 INIT********************************************\n",__func__, __LINE__);
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writel((readl(0xFF600400))|(0x1 << 21), 0xFF600400);
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writel((readl(0xFF6001C8))|(0x1 << 31), 0xFF6001C8);
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} else {
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//printf("********************%s(%d) Add USB520 INIT********************************************\n",__func__, __LINE__);
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writel((readl(0xF0600310))|(0x1 << 1), 0xF0600310);
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writel((readl(0xF06001C8))|(0x1 << 5), 0xF06001C8);
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}
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#endif
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}
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static void axi_bridge_timeout_en(void)
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{
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#if 0
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writel(0x7c, 0xF0012018);
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writel(0x7c, 0xF0013018);
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#endif
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}
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static void nvt_video_dac_init(void)
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{
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/*init video dac verf default to power down */
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int reg = 0;
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reg = readl(0x2f0020004);
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reg |= (0x1 << 9);
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writel(reg, 0x2f0020004);
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reg = readl(0x2f0020070);
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reg |= (0x1 << 26);
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writel(reg, 0x2f0020070);
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reg = readl(0x2f0020074);
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reg |=(0x1 << 13);
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writel(reg, 0x2f0020074);
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reg = readl(0x2f0840044);
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reg |=(0x1 << 14);
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writel(reg, 0x2f0840044);
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}
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int nvt_ivot_hw_init(void)
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{
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ethernet_init();
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axi_bridge_timeout_en();
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usbphy_init();
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nvt_video_dac_init();
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return 0;
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}
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int nvt_ivot_hw_init_early(void)
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{
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otp_init();
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return 0;
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}
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#ifdef CONFIG_NVT_IVOT_DDR_RANGE_SCAN_SUPPORT
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typedef void (*LDR_GENERIC_CB)(void);
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#define JUMP_ADDR 0x2fe000000
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void nvt_ddr_scan(u32 type)
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{
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int reg = 0;
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int ratio = 0;
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uint64_t addr = 0xFE000000;
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int current_el = 0;
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register uint64_t x0 __asm__ ("x0");
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addr = *(UINT32 *)JUMP_ADDR;
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ratio = readl(0x2f00244c0|0x20) | (readl(0x2f00244c0|0x24) << 8) | (readl(0x2f00244c0|0x28) << 16);
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ratio = (ratio*12*8)/131072;
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printf("\nDRAM1_");
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if((readl(0x2f0080008)>>27)&0x1) {
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if((readl(0x2f0080008)>>30)&0x1) {
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printf("DDR4x2_");
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} else {
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printf("DDR4x1_");
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}
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} else {
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printf("DDR3_");
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}
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printf("%d_", ratio);
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if((readl(0x2f0080008)>>28)&0x1) {
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printf("16B\n");
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} else {
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printf("32B\n");
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}
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if ((readl(0x2f0020010)&0xc00000) != 0x0) {
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ratio = readl(0x2f0024840|0x20) | (readl(0x2f0024840|0x24) << 8) | (readl(0x2f0024840|0x28) << 16);
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ratio = (ratio*12*8)/131072;
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printf("\nDRAM2_");
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if((readl(0x2f0090008)>>27)&0x1) {
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if((readl(0x2f0090008)>>30)&0x1) {
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printf("DDR4x2_");
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} else {
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printf("DDR4x1_");
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}
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} else {
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printf("DDR3_");
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}
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printf("%d_", ratio);
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if((readl(0x2f0090008)>>28)&0x1) {
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printf("16B\n");
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} else {
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printf("32B\n");
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}
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}
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//printf("Loader ini ver = 0x%02x\r\n", readl(0xfe20001c));
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// void (*image_entry)(void) = NULL;
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printf("memcpy->[0x%08x]", (int)JUMP_ADDR);
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if (type == 1) {
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memcpy((void *)JUMP_ADDR, ddr_scan_quick, sizeof(ddr_scan_quick));
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printf("->done\n");
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flush_dcache_range(JUMP_ADDR, JUMP_ADDR + sizeof(ddr_scan_quick));
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printf("flush->");
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invalidate_dcache_range(JUMP_ADDR, JUMP_ADDR + roundup(sizeof(ddr_scan_quick), ARCH_DMA_MINALIGN));
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} else if (type == 2) {
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memcpy((void *)JUMP_ADDR, ddr_scan_phy, sizeof(ddr_scan_phy));
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printf("->done\n");
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flush_dcache_range(JUMP_ADDR, JUMP_ADDR + sizeof(ddr_scan_phy));
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printf("flush->");
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invalidate_dcache_range(JUMP_ADDR, JUMP_ADDR + roundup(sizeof(ddr_scan_phy), ARCH_DMA_MINALIGN));
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} else {
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memcpy((void *)JUMP_ADDR, ddr_scan, sizeof(ddr_scan));
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printf("->done\n");
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flush_dcache_range(JUMP_ADDR, JUMP_ADDR + sizeof(ddr_scan));
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printf("flush->");
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invalidate_dcache_range(JUMP_ADDR, JUMP_ADDR + roundup(sizeof(ddr_scan), ARCH_DMA_MINALIGN));
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}
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printf("done\r\n");
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printf("Jump into sram entry point[0x%08x]\n", (int)addr);
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//1. switch register type 0x2Fxxx_xxxx to 0xFxxx_xxxx
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reg = readl(0x2FFE41014);
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reg &= ~(1);
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writel(reg, 0x2FFE41014);
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__asm__ ("mrs x0, CurrentEL;" : : : "%x0");
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current_el = (int)(x0 >> 2);
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printf("Current EL = %d\r\n", (int)current_el);
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if(current_el == 2) {
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printf("Current EL = 2 and use EL1 to execute aarch32\r\n");
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__asm__ volatile ( "MSR SCTLR_EL1, XZR\n"
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"MRS X0, HCR_EL2\n"
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"BIC X0, X0, #(1<<31)\n"
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"MSR HCR_EL2, X0\n"
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"MOV X0, #0b10011\n"
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"MSR SPSR_EL2, X0\n"
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: : :);
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__asm__ volatile (" msr ELR_EL2, %0\n"
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"ERET\n"
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: : "r" (addr));
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} else if(current_el == 3) {
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printf("Current EL = 3 and use EL2 to execute aarch32\r\n");
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__asm__ volatile ( "MSR SCTLR_EL2, XZR\n"
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"MSR HCR_EL2, XZR\n"
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"MRS X0, SCR_EL3\n"
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"BIC X0, X0, #(1<<10)\n"
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"MSR SCR_EL3, x0\n"
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"MOV X0, #0b10011\n"
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"MSR SPSR_EL3, X0\n"
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: : :);
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__asm__ volatile (" msr ELR_EL3, %0\n"
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"ERET\n"
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: : "r" (addr));
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} else if(current_el == 1) {
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printf("Current EL = 1 and use EL0 to execute aarch32 => not support\r\n");
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} else {
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printf("Unknow EL ...\r\n");
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}
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//image_entry = (LDR_GENERIC_CB)(*((unsigned long*)JUMP_ADDR));
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//image_entry();
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}
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#endif
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