157 lines
3.6 KiB
C
157 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <clk.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/printk.h>
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#include "denali.h"
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struct denali_dt_data {
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unsigned int revision;
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unsigned int caps;
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const struct nand_ecc_caps *ecc_caps;
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};
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NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
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512, 8, 15);
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static const struct denali_dt_data denali_socfpga_data = {
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.caps = DENALI_CAP_HW_ECC_FIXUP,
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.ecc_caps = &denali_socfpga_ecc_caps,
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};
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NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
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1024, 8, 16, 24);
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static const struct denali_dt_data denali_uniphier_v5a_data = {
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.caps = DENALI_CAP_HW_ECC_FIXUP |
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DENALI_CAP_DMA_64BIT,
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.ecc_caps = &denali_uniphier_v5a_ecc_caps,
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};
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NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
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1024, 8, 16);
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static const struct denali_dt_data denali_uniphier_v5b_data = {
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.revision = 0x0501,
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.caps = DENALI_CAP_HW_ECC_FIXUP |
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DENALI_CAP_DMA_64BIT,
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.ecc_caps = &denali_uniphier_v5b_ecc_caps,
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};
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static const struct udevice_id denali_nand_dt_ids[] = {
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{
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.compatible = "altr,socfpga-denali-nand",
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.data = (unsigned long)&denali_socfpga_data,
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},
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{
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.compatible = "socionext,uniphier-denali-nand-v5a",
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.data = (unsigned long)&denali_uniphier_v5a_data,
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},
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{
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.compatible = "socionext,uniphier-denali-nand-v5b",
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.data = (unsigned long)&denali_uniphier_v5b_data,
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},
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{ /* sentinel */ }
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};
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static int denali_dt_probe(struct udevice *dev)
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{
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struct denali_nand_info *denali = dev_get_priv(dev);
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const struct denali_dt_data *data;
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struct clk clk, clk_x, clk_ecc;
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struct resource res;
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int ret;
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data = (void *)dev_get_driver_data(dev);
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if (data) {
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denali->revision = data->revision;
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denali->caps = data->caps;
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denali->ecc_caps = data->ecc_caps;
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}
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denali->dev = dev;
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ret = dev_read_resource_byname(dev, "denali_reg", &res);
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if (ret)
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return ret;
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denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
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ret = dev_read_resource_byname(dev, "nand_data", &res);
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if (ret)
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return ret;
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denali->host = devm_ioremap(dev, res.start, resource_size(&res));
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ret = clk_get_by_name(dev, "nand", &clk);
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if (ret)
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_get_by_name(dev, "nand_x", &clk_x);
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if (ret)
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clk_x.dev = NULL;
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ret = clk_get_by_name(dev, "ecc", &clk_ecc);
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if (ret)
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clk_ecc.dev = NULL;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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if (clk_x.dev) {
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ret = clk_enable(&clk_x);
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if (ret)
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return ret;
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}
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if (clk_ecc.dev) {
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ret = clk_enable(&clk_ecc);
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if (ret)
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return ret;
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}
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if (clk_x.dev) {
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denali->clk_rate = clk_get_rate(&clk);
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denali->clk_x_rate = clk_get_rate(&clk_x);
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} else {
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/*
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* Hardcode the clock rates for the backward compatibility.
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* This works for both SOCFPGA and UniPhier.
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*/
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dev_notice(dev,
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"necessary clock is missing. default clock rates are used.\n");
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denali->clk_rate = 50000000;
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denali->clk_x_rate = 200000000;
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}
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return denali_init(denali);
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}
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U_BOOT_DRIVER(denali_nand_dt) = {
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.name = "denali-nand-dt",
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.id = UCLASS_MISC,
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.of_match = denali_nand_dt_ids,
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.probe = denali_dt_probe,
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.priv_auto_alloc_size = sizeof(struct denali_nand_info),
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};
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void board_nand_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(denali_nand_dt),
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&dev);
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if (ret && ret != -ENODEV)
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pr_err("Failed to initialize Denali NAND controller. (error %d)\n",
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ret);
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}
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