119 lines
3.7 KiB
C
119 lines
3.7 KiB
C
/*
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* arch/arm/mach-ep93xx/dma.c
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*
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* Platform support code for the EP93xx dmaengine driver.
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*
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* Copyright (C) 2011 Mika Westerberg
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*
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* This work is based on the original dma-m2p implementation with
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* following copyrights:
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright (C) 2006 Applied Data Systems
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* Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include <mach/hardware.h>
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#include "soc.h"
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#define DMA_CHANNEL(_name, _base, _irq) \
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{ .name = (_name), .base = (_base), .irq = (_irq) }
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/*
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* DMA M2P channels.
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*
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* On the EP93xx chip the following peripherals my be allocated to the 10
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* Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
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*
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* I2S contains 3 Tx and 3 Rx DMA Channels
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* AAC contains 3 Tx and 3 Rx DMA Channels
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* UART1 contains 1 Tx and 1 Rx DMA Channels
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* UART2 contains 1 Tx and 1 Rx DMA Channels
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* UART3 contains 1 Tx and 1 Rx DMA Channels
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* IrDA contains 1 Tx and 1 Rx DMA Channels
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*
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* Registers are mapped statically in ep93xx_map_io().
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*/
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static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
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DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
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DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
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DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
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DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
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DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
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DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
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DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
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DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
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DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
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DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
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};
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static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
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.channels = ep93xx_dma_m2p_channels,
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.num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
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};
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static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
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static struct platform_device ep93xx_dma_m2p_device = {
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.name = "ep93xx-dma-m2p",
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.id = -1,
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.dev = {
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.platform_data = &ep93xx_dma_m2p_data,
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.dma_mask = &ep93xx_dma_m2p_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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/*
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* DMA M2M channels.
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*
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* There are 2 M2M channels which support memcpy/memset and in addition simple
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* hardware requests from/to SSP and IDE. We do not implement an external
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* hardware requests.
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*
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* Registers are mapped statically in ep93xx_map_io().
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*/
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static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
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DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
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DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
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};
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static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
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.channels = ep93xx_dma_m2m_channels,
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.num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
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};
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static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
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static struct platform_device ep93xx_dma_m2m_device = {
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.name = "ep93xx-dma-m2m",
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.id = -1,
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.dev = {
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.platform_data = &ep93xx_dma_m2m_data,
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.dma_mask = &ep93xx_dma_m2m_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static int __init ep93xx_dma_init(void)
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{
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platform_device_register(&ep93xx_dma_m2p_device);
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platform_device_register(&ep93xx_dma_m2m_device);
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return 0;
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}
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arch_initcall(ep93xx_dma_init);
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