231 lines
6.3 KiB
Plaintext
231 lines
6.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's Exynos5 SoC series common device tree source
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*
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* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
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* SoCs from Exynos5 series can include this file and provide values for SoCs
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* specfic bindings.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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serial0 = &serial_0;
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serial1 = &serial_1;
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serial2 = &serial_2;
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serial3 = &serial_3;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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sromc: memory-controller@12250000 {
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compatible = "samsung,exynos4210-srom";
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reg = <0x12250000 0x14>;
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};
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combiner: interrupt-controller@10440000 {
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compatible = "samsung,exynos4210-combiner";
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#interrupt-cells = <2>;
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interrupt-controller;
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samsung,combiner-nr = <32>;
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reg = <0x10440000 0x1000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@10481000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10481000 0x1000>,
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<0x10482000 0x2000>,
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<0x10484000 0x2000>,
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<0x10486000 0x2000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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sysreg_system_controller: syscon@10050000 {
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compatible = "samsung,exynos5-sysreg", "syscon";
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reg = <0x10050000 0x5000>;
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};
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serial_0: serial@12c00000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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};
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serial_1: serial@12c10000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C10000 0x100>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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};
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serial_2: serial@12c20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C20000 0x100>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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};
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serial_3: serial@12c30000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C30000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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};
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i2c_0: i2c@12c60000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C60000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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status = "disabled";
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};
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i2c_1: i2c@12c70000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C70000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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status = "disabled";
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};
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i2c_2: i2c@12c80000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C80000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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status = "disabled";
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};
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i2c_3: i2c@12c90000 {
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compatible = "samsung,s3c2440-i2c";
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reg = <0x12C90000 0x100>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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status = "disabled";
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};
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pwm: pwm@12dd0000 {
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compatible = "samsung,exynos4210-pwm";
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reg = <0x12DD0000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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samsung,pwm-outputs = <0>, <1>, <2>, <3>;
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#pwm-cells = <3>;
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};
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rtc: rtc@101e0000 {
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compatible = "samsung,s3c6410-rtc";
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reg = <0x101E0000 0x100>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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fimd: fimd@14400000 {
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compatible = "samsung,exynos5250-fimd";
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interrupt-parent = <&combiner>;
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reg = <0x14400000 0x40000>;
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interrupt-names = "fifo", "vsync", "lcd_sys";
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interrupts = <18 4>, <18 5>, <18 6>;
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samsung,sysreg = <&sysreg_system_controller>;
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status = "disabled";
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};
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dp: dp-controller@145b0000 {
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compatible = "samsung,exynos5-dp";
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reg = <0x145B0000 0x1000>;
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interrupts = <10 3>;
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interrupt-parent = <&combiner>;
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status = "disabled";
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};
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sss: sss@10830000 {
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compatible = "samsung,exynos4210-secss";
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reg = <0x10830000 0x300>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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};
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prng: rng@10830400 {
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compatible = "samsung,exynos5250-prng";
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reg = <0x10830400 0x200>;
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};
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trng: rng@10830600 {
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compatible = "samsung,exynos5250-trng";
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reg = <0x10830600 0x100>;
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};
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g2d: g2d@10850000 {
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compatible = "samsung,exynos5250-g2d";
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reg = <0x10850000 0x1000>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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};
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