202 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			202 lines
		
	
	
		
			4.2 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Broadcom BCM63138 DSL SoCs Device Tree
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|  */
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| 
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| #include <dt-bindings/interrupt-controller/arm-gic.h>
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| #include <dt-bindings/interrupt-controller/irq.h>
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| 
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| #include "skeleton.dtsi"
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| 
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| / {
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| 	compatible = "brcm,bcm63138";
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| 	model = "Broadcom BCM63138 DSL SoC";
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| 	interrupt-parent = <&gic>;
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| 
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| 	aliases {
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| 		uart0 = &serial0;
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| 		uart1 = &serial1;
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| 	};
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| 
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| 	cpus {
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		cpu@0 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			next-level-cache = <&L2>;
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| 			reg = <0>;
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| 			enable-method = "brcm,bcm63138";
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| 		};
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| 
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| 		cpu@1 {
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| 			device_type = "cpu";
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| 			compatible = "arm,cortex-a9";
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| 			next-level-cache = <&L2>;
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| 			reg = <1>;
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| 			enable-method = "brcm,bcm63138";
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| 			resets = <&pmb0 4 1>;
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| 		};
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| 	};
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| 
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| 	clocks {
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| 		#address-cells = <1>;
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| 		#size-cells = <0>;
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| 
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| 		/* UBUS peripheral clock */
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| 		periph_clk: periph_clk {
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| 			#clock-cells = <0>;
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| 			compatible = "fixed-clock";
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| 			clock-frequency = <50000000>;
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| 			clock-output-names = "periph";
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| 		};
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| 
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| 		/* peripheral clock for system timer */
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| 		axi_clk: axi_clk {
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| 			#clock-cells = <0>;
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| 			compatible = "fixed-factor-clock";
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| 			clocks = <&armpll>;
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| 			clock-div = <2>;
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| 			clock-mult = <1>;
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| 		};
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| 
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| 		/* APB bus clock */
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| 		apb_clk: apb_clk {
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| 			#clock-cells = <0>;
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| 			compatible = "fixed-factor-clock";
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| 			clocks = <&armpll>;
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| 			clock-div = <4>;
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| 			clock-mult = <1>;
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| 		};
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| 	};
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| 
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| 	/* ARM bus */
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| 	axi@80000000 {
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| 		compatible = "simple-bus";
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| 		ranges = <0 0x80000000 0x784000>;
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| 		#address-cells = <1>;
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| 		#size-cells = <1>;
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| 
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| 		L2: cache-controller@1d000 {
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| 			compatible = "arm,pl310-cache";
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| 			reg = <0x1d000 0x1000>;
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| 			cache-unified;
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| 			cache-level = <2>;
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| 			cache-size = <524288>;
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| 			cache-sets = <1024>;
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| 			cache-line-size = <32>;
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| 			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
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| 		};
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| 
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| 		scu: scu@1e000 {
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| 			compatible = "arm,cortex-a9-scu";
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| 			reg = <0x1e000 0x100>;
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| 		};
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| 
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| 		gic: interrupt-controller@1e100 {
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| 			compatible = "arm,cortex-a9-gic";
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| 			reg = <0x1f000 0x1000
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| 				0x1e100 0x100>;
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| 			#interrupt-cells = <3>;
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| 			#address-cells = <0>;
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| 			interrupt-controller;
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| 		};
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| 
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| 		global_timer: timer@1e200 {
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| 			compatible = "arm,cortex-a9-global-timer";
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| 			reg = <0x1e200 0x20>;
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| 			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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| 			clocks = <&axi_clk>;
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| 		};
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| 
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| 		local_timer: local-timer@1e600 {
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| 			compatible = "arm,cortex-a9-twd-timer";
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| 			reg = <0x1e600 0x20>;
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| 			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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| 						  IRQ_TYPE_EDGE_RISING)>;
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| 			clocks = <&axi_clk>;
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| 		};
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| 
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| 		twd_watchdog: watchdog@1e620 {
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| 			compatible = "arm,cortex-a9-twd-wdt";
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| 			reg = <0x1e620 0x20>;
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| 			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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| 						  IRQ_TYPE_LEVEL_HIGH)>;
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| 		};
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| 
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| 		armpll: armpll {
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| 			#clock-cells = <0>;
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| 			compatible = "brcm,bcm63138-armpll";
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| 			clocks = <&periph_clk>;
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| 			reg = <0x20000 0xf00>;
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| 		};
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| 
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| 		pmb0: reset-controller@4800c0 {
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| 			compatible = "brcm,bcm63138-pmb";
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| 			reg = <0x4800c0 0x10>;
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| 			#reset-cells = <2>;
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| 		};
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| 
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| 		pmb1: reset-controller@4800e0 {
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| 			compatible = "brcm,bcm63138-pmb";
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| 			reg = <0x4800e0 0x10>;
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| 			#reset-cells = <2>;
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| 		};
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| 	};
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| 
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| 	/* Legacy UBUS base */
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| 	ubus@fffe8000 {
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| 		compatible = "simple-bus";
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| 		#address-cells = <1>;
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| 		#size-cells = <1>;
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| 		ranges = <0 0xfffe8000 0x8100>;
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| 
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| 		timer: timer@80 {
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| 			compatible = "brcm,bcm6328-timer", "syscon";
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| 			reg = <0x80 0x3c>;
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| 		};
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| 
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| 		serial0: serial@600 {
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| 			compatible = "brcm,bcm6345-uart";
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| 			reg = <0x600 0x1b>;
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| 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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| 			clocks = <&periph_clk>;
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| 			clock-names = "periph";
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| 			status = "disabled";
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| 		};
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| 
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| 		serial1: serial@620 {
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| 			compatible = "brcm,bcm6345-uart";
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| 			reg = <0x620 0x1b>;
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| 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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| 			clocks = <&periph_clk>;
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| 			clock-names = "periph";
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| 			status = "disabled";
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| 		};
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| 
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| 		nand: nand@2000 {
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| 			#address-cells = <1>;
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| 			#size-cells = <0>;
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| 			compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
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| 			reg = <0x2000 0x600>, <0xf0 0x10>;
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| 			reg-names = "nand", "nand-int-base";
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| 			status = "disabled";
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| 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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| 			interrupt-names = "nand";
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| 		};
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| 
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| 		bootlut: bootlut@8000 {
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| 			compatible = "brcm,bcm63138-bootlut";
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| 			reg = <0x8000 0x50>;
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| 		};
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| 
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| 		reboot {
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| 			compatible = "syscon-reboot";
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| 			regmap = <&timer>;
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| 			offset = <0x34>;
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| 			mask = <1>;
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| 		};
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| 	};
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| };
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