219 lines
10 KiB
C
Executable File
219 lines
10 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0
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/*
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* NVT UART header for NA51055/NA51084 platform
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*
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* This file is the internal header file that defines the variables,
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* structures and function prototypes of UART module.
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*
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* @file nvt_serial.h
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*
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* Copyright Novatek Microelectronics Corp. 2020. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _NVT_SERIAL_H
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#define _NVT_SERIAL_H
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#define NVT_FR 1 /* A flag to distinguish between different platforms */
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#define UART_MCR_AFC 0x40 /* Enable NVT auto-RTS/CTS */
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/************************
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* UART Registers *
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************************/
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/*
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* 0x00 Receive Buffer Register (RBR), when DLAB=0 read
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* Transmit Holding Register (THR), when DLAB=0 write
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* Baud Rate Divisor Latch LSB (DLL), when DLAB=1
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*/
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#define UART_RBR_REG 0x00 /* Receive data port */
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#define UART_THR_REG 0x00 /* Transmit data port */
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#define UART_DLL_REG 0x00
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#define DLL_MASK GENMASK(7, 0) /* Baud rate Divisor Latch Least significant byte */
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#define UART_DLR_MAX 0xFFFF /* Divisor Latch Register Max value */
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#define UART_DLR_MIN 0x0001 /* Divisor Latch Register Min value */
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/*
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* 0x04 Interrupt Enable Register (IER), when DLAB=0
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* Baud Rate Divisor Latch MSB (DLM), when DLAB=1
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*/
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#define UART_IER_REG 0x04
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#define RDA_INTEN_BIT BIT(0) /* Received Data Available Interrupt enable */
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#define THR_EMPTY_INTEN_BIT BIT(1) /* Transmitter Holding Register Empty Interrupt enable */
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#define RLS_INTEN_BIT BIT(2) /* Receiver Line Status Interrupt enable */
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#define UART_DLM_REG 0x04
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#define DLM_MASK GENMASK(7, 0) /* Baud rate Divisor Latch Most significant byte */
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/*
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* 0x08 Interrupt ID Register (IIR), when DLAB=0 read
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* FIFO Control Register (FCR), when DLAB=0 write
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* Prescaler Register (PSR), when DLAB=1
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*/
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#define UART_IIR_REG 0x08
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#define UART_IIR_INT_ID_MASK GENMASK(3, 0) /* Interrupt ID mask */
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#define _UART_IIR_INT_NONE 0x1 /* None */
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#define _UART_IIR_INT_RLS 0x6 /* Receiver Line Status */
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#define _UART_IIR_INT_RDR 0x4 /* Received Data Ready */
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#define _UART_IIR_INT_CRT 0xC /* Character Reception Timeout */
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#define _UART_IIR_INT_THRE 0x2 /* Transmitter Holding Register Empty */
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#define FIFO_MODE_ENABLED_BIT BIT(7) /* This bit is set when FCR[0] is set as 1 */
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#define UART_FCR_REG 0x08
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#define FIFO_EN_BIT BIT(0) /* FIFO enable (Do not change this bit when TX_DMA_EN or RX_DMA_EN bit is set) */
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#define RX_FIFO_RESET_BIT BIT(1) /* Rx FIFO Reset */
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#define TX_FIFO_RESET_BIT BIT(2) /* Tx FIFO Reset */
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#define RXFIFO_TRGL_MASK GENMASK(7, 6) /* Rx trigger level for data ready interrupt */
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#define _UART_FCR_RX_TRIGGER_SHIFT 6
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#define _UART_FCR_RX_TRIGGER_LEVEL_0 0x0 /* character = 1(16 FIFO) and 1 (64 FIFO) */
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#define _UART_FCR_RX_TRIGGER_LEVEL_1 0x1 /* character = 4(16 FIFO) and 16 (64 FIFO) */
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#define _UART_FCR_RX_TRIGGER_LEVEL_2 0x2 /* character = 8(16 FIFO) and 48 (64 FIFO) */
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#define _UART_FCR_RX_TRIGGER_LEVEL_3 0x3 /* character = 14(16 FIFO) and 56 (64 FIFO) */
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#define UART_PSR_REG 0x08
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#define PSR_MASK GENMASK(4, 0) /* Prescaler Register */
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/* 0x0C Line Control Register (LCR) */
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#define UART_LCR_REG 0x0C
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#define _WL_L5 0x0 /* Char Length 5 */
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#define _WL_L6 0x1 /* Char Length 6 */
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#define _WL_L7 0x2 /* Char Length 7 */
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#define _WL_L8 0x3 /* Char Length 8 */
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#define STOP_BIT BIT(2) /* Stop Bits */
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#define _UART_LCR_PARITY_SHIFT 3 /* LCR PARITY SHIFT BIT */
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#define _UART_PARITY_NONE 0x0 /* No parity checking */
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#define _UART_PARITY_ODD 0x1 /* Odd parity */
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#define _UART_PARITY_EVEN 0x3 /* Even parity */
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#define _UART_PARITY_ONE 0x5 /* One parity */
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#define _UART_PARITY_ZERO 0x7 /* Zero parity */
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#define SET_BREAK_BIT BIT(6) /* Causes a break condition to be transmitted (Only Tx) */
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#define DLAB_BIT BIT(7) /* Divisor Latch Access Bit (DLAB) */
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/*
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* 0x14 Line Status Register (LSR), when read
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* Testing Register (TST), when write
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*/
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#define UART_LSR_REG 0x14
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#define DATA_READY_BIT BIT(0) /* Data ready */
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#define OVERRUN_ERR_BIT BIT(1) /* Overrun error (PIO Only) */
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#define PARITY_ERR_BIT BIT(2) /* Parity error */
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#define FRAMING_ERR_BIT BIT(3) /* Framing error */
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#define BREAK_INT_BIT BIT(4) /* Break interrupt */
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#define THR_EMPTY_BIT BIT(5) /* THR empty */
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#define TRANSMITTER_EMPTY_BIT BIT(6) /* Transmitter empty */
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#define BOTH_EMPTY_BIT (THR_EMPTY_BIT | TRANSMITTER_EMPTY_BIT)
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#define FIFO_DATA_ERR_BIT BIT(7) /* FIFO data error */
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#define UART_TST_REG 0x14
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#define TEST_PAR_ERR_BIT BIT(0) /* Generates incorrect parity during UART transmission */
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#define TEST_FRM_ERR_BIT BIT(1) /* Generates a logic 0 STOP bit during UART transmission */
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#define TEST_BAUDGEN_BIT BIT(2) /* Just to improve baud rate generator toggle rate */
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/* 0x1C Scratch Pad Register (SPR) */
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#define UART_SPR_REG 0x1C
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#define USER_DATA_MASK GENMASK(7, 0) /* Used by programmer to hold data temporarily */
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/*************************
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* UART2 Registers *
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*************************/
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/* 0x10 MODEN Control Register */
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#define UART_MCR_REG 0x10
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#define LOOP_BIT BIT(4)
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#define HW_FLOW_CTRL_BIT BIT(6) /* Hardware Flow Control */
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/* 0x20 RS485 Register */
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#define UART_RS485_REG 0x20
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#define ENABLE_BIT BIT(0) /* RS485 mode is enable, RTS signal will be operated as DE signal */
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#define SETUP_TIME_MASK GENMASK(15, 4) /* Setup time between DE rising and first Tx signal */
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#define _UART_RS485_SETUP_TIME_SHIFT 4
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#define HOLD_TIME_MASK GENMASK(31, 20) /* Setup time between DE falling and first Tx signal */
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#define _UART_RS485_HOLD_TIME_SHIFT 20
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/* 0x80 Tx DMA Starting Address Register */
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#define UART_TX_DMA_ADDR_REG 0x80
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#define TX_DMA_ADDRESS_MASK GENMASK(30, 0)
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/* 0x84 Tx DMA Starting SIZE Register */
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#define UART_TX_DMA_SIZE_REG 0x84
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#define TX_DMA_SIZE_MASK GENMASK(19, 0)
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/* 0x88, Tx DMA Current Address Register */
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#define UART_TX_CUR_ADDR_REG 0x88
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#define TX_CUR_ADDRESS_MASK GENMASK(30, 0)
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/* 0x8C, Tx DMA Control Register */
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#define UART_TX_DMA_CTRL_REG 0x8C
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#define TX_DMA_EN_BIT BIT(0)
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/* 0x90, Rx DMA Starting Address Register */
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#define UART_RX_DMA_ADDR_REG 0x90
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#define RX_DMA_ADDRESS_MASK GENMASK(30, 0)
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/* 0x94, Rx DMA Starting SIZE Register */
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#define UART_RX_DMA_SIZE_REG 0x94
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#define RX_DMA_SIZE_MASK GENMASK(19, 0)
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/* 0x98, Rx DMA Current Address Register */
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#define UART_RX_CUR_ADDR_REG 0x98
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#define RX_CUR_ADDRESS_MASK GENMASK(30, 0)
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/* 0x9C, Rx DMA Control Register */
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#define UART_RX_DMA_CTRL_REG 0x9C
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#define RX_DMA_EN_BIT BIT(0)
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/* 0xA0, DMA Interrupt Control Register */
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#define UART_DMA_INT_CTRL_REG 0xA0
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#define TX_DMA_DONE_INTEN_BIT BIT(0)
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#define RX_DMA_DONE_INTEN_BIT BIT(8)
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#define RX_DMA_ERR_INTEN_BIT BIT(9)
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/* 0xA4, DMA Interrupt Status Register */
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#define UART_DMA_INT_STS_REG 0xA4
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#define TX_DMA_DONE_BIT BIT(0)
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#define RX_DMA_DONE_BIT BIT(8)
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#define RX_DMA_ERR_BIT BIT(9)
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#define DMA_OVERRUN_ERR_BIT BIT(16)
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#define DMA_PARITY_ERR_BIT BIT(17)
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#define DMA_FRAMING_ERR_BIT BIT(18)
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#define DMA_BREAK_ERR_BIT BIT(19)
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struct nvt_port {
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struct uart_port uart;
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char name[16];
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struct spinlock write_lock;
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struct clk *clk;
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unsigned int baud;
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unsigned int tx_loadsz; /* transmit fifo load size */
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unsigned int hw_flowctrl; /* hardware flow contol */
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unsigned int rx_trig_level; /* rx fifo trigger level */
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unsigned int rs485_en; /* rs485 feature */
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unsigned int rs485_delay_before_send;
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unsigned int rs485_delay_after_send;
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/*
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* Some bits in registers are cleared on a read, so they must
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* be saved whenever the register is read, but the bits will not
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* be immediately processed.
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*/
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unsigned int lsr_break_flag;
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unsigned char lsr_saved_flags;
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/* DMA feature */
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unsigned int tx_dma_en;
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unsigned int rx_dma_en;
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unsigned char *tx_virt_addr;
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unsigned char *rx_virt_addr;
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dma_addr_t tx_dma_addr;
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dma_addr_t rx_dma_addr;
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unsigned int tx_size;
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unsigned int rx_size;
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struct work_struct rx_dma_work;
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};
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#endif
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