148 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
			
		
		
	
	
			148 lines
		
	
	
		
			4.6 KiB
		
	
	
	
		
			Plaintext
		
	
	
	
	
	
| Device-Tree bindings for LVDS Display Bridge (ldb)
 | |
| 
 | |
| LVDS Display Bridge
 | |
| ===================
 | |
| 
 | |
| The LVDS Display Bridge device tree node contains up to two lvds-channel
 | |
| nodes describing each of the two LVDS encoder channels of the bridge.
 | |
| 
 | |
| Required properties:
 | |
|  - #address-cells : should be <1>
 | |
|  - #size-cells : should be <0>
 | |
|  - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
 | |
|                 Both LDB versions are similar, but i.MX6 has an additional
 | |
|                 multiplexer in the front to select any of the four IPU display
 | |
|                 interfaces as input for each LVDS channel.
 | |
|  - gpr : should be <&gpr> on i.MX53 and i.MX6q.
 | |
|          The phandle points to the iomuxc-gpr region containing the LVDS
 | |
|          control register.
 | |
| - clocks, clock-names : phandles to the LDB divider and selector clocks and to
 | |
|                         the display interface selector clocks, as described in
 | |
|                         Documentation/devicetree/bindings/clock/clock-bindings.txt
 | |
|         The following clocks are expected on i.MX53:
 | |
|                 "di0_pll" - LDB LVDS channel 0 mux
 | |
|                 "di1_pll" - LDB LVDS channel 1 mux
 | |
|                 "di0" - LDB LVDS channel 0 gate
 | |
|                 "di1" - LDB LVDS channel 1 gate
 | |
|                 "di0_sel" - IPU1 DI0 mux
 | |
|                 "di1_sel" - IPU1 DI1 mux
 | |
|         On i.MX6q the following additional clocks are needed:
 | |
|                 "di2_sel" - IPU2 DI0 mux
 | |
|                 "di3_sel" - IPU2 DI1 mux
 | |
|         The needed clock numbers for each are documented in
 | |
|         Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
 | |
|         Documentation/devicetree/bindings/clock/imx6q-clock.txt.
 | |
| 
 | |
| Optional properties:
 | |
|  - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
 | |
|  - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
 | |
|                not used on i.MX6q
 | |
|  - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
 | |
|    be configured - one input will be distributed on both outputs in dual
 | |
|    channel mode
 | |
| 
 | |
| LVDS Channel
 | |
| ============
 | |
| 
 | |
| Each LVDS Channel has to contain either an of graph link to a panel device node
 | |
| or a display-timings node that describes the video timings for the connected
 | |
| LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
 | |
| 
 | |
| Required properties:
 | |
|  - reg : should be <0> or <1>
 | |
|  - port: Input and output port nodes with endpoint definitions as defined in
 | |
|    Documentation/devicetree/bindings/graph.txt.
 | |
|    On i.MX5, the internal two-input-multiplexer is used. Due to hardware
 | |
|    limitations, only one input port (port@[0,1]) can be used for each channel
 | |
|    (lvds-channel@[0,1], respectively).
 | |
|    On i.MX6, there should be four input ports (port@[0-3]) that correspond
 | |
|    to the four LVDS multiplexer inputs.
 | |
|    A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
 | |
|    to a panel input port. Optionally, the output port can be left out if
 | |
|    display-timings are used instead.
 | |
| 
 | |
| Optional properties (required if display-timings are used):
 | |
|  - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
 | |
|  - display-timings : A node that describes the display timings as defined in
 | |
|    Documentation/devicetree/bindings/display/panel/display-timing.txt.
 | |
|  - fsl,data-mapping : should be "spwg" or "jeida"
 | |
|                       This describes how the color bits are laid out in the
 | |
|                       serialized LVDS signal.
 | |
|  - fsl,data-width : should be <18> or <24>
 | |
| 
 | |
| example:
 | |
| 
 | |
| gpr: iomuxc-gpr@53fa8000 {
 | |
| 	/* ... */
 | |
| };
 | |
| 
 | |
| ldb: ldb@53fa8008 {
 | |
| 	#address-cells = <1>;
 | |
| 	#size-cells = <0>;
 | |
| 	compatible = "fsl,imx53-ldb";
 | |
| 	gpr = <&gpr>;
 | |
| 	clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 | |
| 		 <&clks IMX5_CLK_LDB_DI1_SEL>,
 | |
| 		 <&clks IMX5_CLK_IPU_DI0_SEL>,
 | |
| 		 <&clks IMX5_CLK_IPU_DI1_SEL>,
 | |
| 		 <&clks IMX5_CLK_LDB_DI0_GATE>,
 | |
| 		 <&clks IMX5_CLK_LDB_DI1_GATE>;
 | |
| 	clock-names = "di0_pll", "di1_pll",
 | |
| 		      "di0_sel", "di1_sel",
 | |
| 		      "di0", "di1";
 | |
| 
 | |
| 	/* Using an of-graph endpoint link to connect the panel */
 | |
| 	lvds-channel@0 {
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 		reg = <0>;
 | |
| 
 | |
| 		port@0 {
 | |
| 			reg = <0>;
 | |
| 
 | |
| 			lvds0_in: endpoint {
 | |
| 				remote-endpoint = <&ipu_di0_lvds0>;
 | |
| 			};
 | |
| 		};
 | |
| 
 | |
| 		port@2 {
 | |
| 			reg = <2>;
 | |
| 
 | |
| 			lvds0_out: endpoint {
 | |
| 				remote-endpoint = <&panel_in>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| 
 | |
| 	/* Using display-timings and fsl,data-mapping/width instead */
 | |
| 	lvds-channel@1 {
 | |
| 		#address-cells = <1>;
 | |
| 		#size-cells = <0>;
 | |
| 		reg = <1>;
 | |
| 		fsl,data-mapping = "spwg";
 | |
| 		fsl,data-width = <24>;
 | |
| 
 | |
| 		display-timings {
 | |
| 			/* ... */
 | |
| 		};
 | |
| 
 | |
| 		port@1 {
 | |
| 			reg = <1>;
 | |
| 
 | |
| 			lvds1_in: endpoint {
 | |
| 				remote-endpoint = <&ipu_di1_lvds1>;
 | |
| 			};
 | |
| 		};
 | |
| 	};
 | |
| };
 | |
| 
 | |
| panel: lvds-panel {
 | |
| 	/* ... */
 | |
| 
 | |
| 	port {
 | |
| 		panel_in: endpoint {
 | |
| 			remote-endpoint = <&lvds0_out>;
 | |
| 		};
 | |
| 	};
 | |
| };
 | 
