1007 lines
28 KiB
Plaintext
1007 lines
28 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a77995 SoC
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*
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* Copyright (C) 2016 Renesas Electronics Corp.
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* Copyright (C) 2017 Glider bvba
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*/
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#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a77995-sysc.h>
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/ {
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compatible = "renesas,r8a77995";
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#address-cells = <2>;
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#size-cells = <2>;
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a53_0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0>;
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device_type = "cpu";
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power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
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next-level-cache = <&L2_CA53>;
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enable-method = "psci";
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};
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L2_CA53: cache-controller-1 {
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compatible = "cache";
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power-domains = <&sysc R8A77995_PD_CA53_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu_a53 {
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compatible = "arm,cortex-a53-pmu";
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interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rwdt: watchdog@e6020000 {
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compatible = "renesas,r8a77995-wdt",
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"renesas,rcar-gen3-wdt";
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reg = <0 0xe6020000 0 0x0c>;
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clocks = <&cpg CPG_MOD 402>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 402>;
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status = "disabled";
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6050000 0 0x50>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 0 9>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 912>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 912>;
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};
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6051000 0 0x50>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 32 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 911>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 911>;
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};
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6052000 0 0x50>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 64 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 910>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 910>;
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};
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6053000 0 0x50>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 96 10>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 909>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 909>;
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};
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6054000 0 0x50>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 128 32>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 908>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 908>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055000 0 0x50>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 160 21>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 907>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 907>;
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};
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gpio6: gpio@e6055400 {
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compatible = "renesas,gpio-r8a77995",
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"renesas,rcar-gen3-gpio";
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reg = <0 0xe6055400 0 0x50>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-ranges = <&pfc 0 192 14>;
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#interrupt-cells = <2>;
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interrupt-controller;
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clocks = <&cpg CPG_MOD 906>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 906>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a77995";
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reg = <0 0xe6060000 0 0x508>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a77995-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a77995-rst";
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reg = <0 0xe6160000 0 0x0200>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a77995-sysc";
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reg = <0 0xe6180000 0 0x0400>;
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#power-domain-cells = <1>;
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};
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thermal: thermal@e6190000 {
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compatible = "renesas,thermal-r8a77995";
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reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 522>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 522>;
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#thermal-sensor-cells = <0>;
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};
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intc_ex: interrupt-controller@e61c0000 {
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compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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hscif0: serial@e6540000 {
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compatible = "renesas,hscif-r8a77995",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe6540000 0 0x60>;
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interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 520>,
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<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x31>, <&dmac1 0x30>,
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<&dmac2 0x31>, <&dmac2 0x30>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 520>;
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status = "disabled";
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};
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hscif3: serial@e66a0000 {
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compatible = "renesas,hscif-r8a77995",
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"renesas,rcar-gen3-hscif",
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"renesas,hscif";
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reg = <0 0xe66a0000 0 0x60>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 517>,
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<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x37>, <&dmac0 0x36>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 517>;
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status = "disabled";
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};
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i2c0: i2c@e6500000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77995",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6500000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 931>;
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dmas = <&dmac1 0x91>, <&dmac1 0x90>,
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<&dmac2 0x91>, <&dmac2 0x90>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c1: i2c@e6508000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77995",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 930>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 930>;
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dmas = <&dmac1 0x93>, <&dmac1 0x92>,
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<&dmac2 0x93>, <&dmac2 0x92>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c2: i2c@e6510000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77995",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe6510000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 929>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 929>;
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dmas = <&dmac1 0x95>, <&dmac1 0x94>,
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<&dmac2 0x95>, <&dmac2 0x94>;
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dma-names = "tx", "rx", "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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i2c3: i2c@e66d0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,i2c-r8a77995",
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"renesas,rcar-gen3-i2c";
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reg = <0 0xe66d0000 0 0x40>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 928>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 928>;
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dmas = <&dmac0 0x97>, <&dmac0 0x96>;
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dma-names = "tx", "rx";
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i2c-scl-internal-delay-ns = <6>;
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status = "disabled";
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};
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canfd: can@e66c0000 {
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compatible = "renesas,r8a77995-canfd",
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"renesas,rcar-gen3-canfd";
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reg = <0 0xe66c0000 0 0x8000>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 914>,
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<&cpg CPG_CORE R8A77995_CLK_CANFD>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
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assigned-clock-rates = <40000000>;
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 914>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x10000>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 219>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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dmac1: dma-controller@e7300000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe7300000 0 0x10000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
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dmac2: dma-controller@e7310000 {
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compatible = "renesas,dmac-r8a77995",
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"renesas,rcar-dmac";
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reg = <0 0xe7310000 0 0x10000>;
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interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7";
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clocks = <&cpg CPG_MOD 217>;
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clock-names = "fck";
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power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
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resets = <&cpg 217>;
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#dma-cells = <1>;
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dma-channels = <8>;
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};
|
|
|
|
ipmmu_ds0: mmu@e6740000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe6740000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ds1: mmu@e7740000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe7740000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_hc: mmu@e6570000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe6570000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mm: mmu@e67b0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe67b0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mp: mmu@ec670000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xec670000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_pv0: mmu@fd800000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfd800000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_rt: mmu@ffc80000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xffc80000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vc0: mmu@fe6b0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfe6b0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi0: mmu@febd0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfebd0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vp0: mmu@fe990000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfe990000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a77995",
|
|
"renesas,etheravb-rcar-gen3";
|
|
reg = <0 0xe6800000 0 0x800>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 812>;
|
|
phy-mode = "rgmii";
|
|
iommus = <&ipmmu_ds0 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can0: can@e6c30000 {
|
|
compatible = "renesas,can-r8a77995",
|
|
"renesas,rcar-gen3-can";
|
|
reg = <0 0xe6c30000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>,
|
|
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e6c38000 {
|
|
compatible = "renesas,can-r8a77995",
|
|
"renesas,rcar-gen3-can";
|
|
reg = <0 0xe6c38000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>,
|
|
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 207>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
|
<&dmac2 0x51>, <&dmac2 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 207>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 206>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
|
<&dmac2 0x53>, <&dmac2 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 206>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e88000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e88000 0 64>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 310>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
|
<&dmac2 0x13>, <&dmac2 0x12>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 310>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 204>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 203>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6f30000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6f30000 0 64>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 202>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
|
|
<&dmac2 0x5b>, <&dmac2 0x5a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 202>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6e90000 0 0x64>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 211>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6ea0000 0 0x64>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 210>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 210>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c00000 0 0x64>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 209>;
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 209>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c10000 0 0x64>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 208>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin4: video@e6ef4000 {
|
|
compatible = "renesas,vin-r8a77995";
|
|
reg = <0 0xe6ef4000 0 0x1000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 807>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 807>;
|
|
renesas,id = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ohci0: usb@ee080000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0xee080000 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
phys = <&usb2_phy0>;
|
|
phy-names = "usb";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@ee080100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0xee080100 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
phys = <&usb2_phy0>;
|
|
phy-names = "usb";
|
|
companion = <&ohci0>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy0: usb-phy@ee080200 {
|
|
compatible = "renesas,usb2-phy-r8a77995",
|
|
"renesas,rcar-gen3-usb2-phy";
|
|
reg = <0 0xee080200 0 0x700>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: sd@ee140000 {
|
|
compatible = "renesas,sdhi-r8a77995",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 312>;
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 312>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@f1010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1010000 0 0x1000>,
|
|
<0x0 0xf1020000 0 0x20000>,
|
|
<0x0 0xf1040000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x20000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD 408>;
|
|
clock-names = "clk";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 408>;
|
|
};
|
|
|
|
vspbs: vsp@fe960000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfe960000 0 0x8000>;
|
|
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 627>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 627>;
|
|
renesas,fcp = <&fcpvb0>;
|
|
};
|
|
|
|
vspd0: vsp@fea20000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea20000 0 0x5000>;
|
|
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
renesas,fcp = <&fcpvd0>;
|
|
};
|
|
|
|
vspd1: vsp@fea28000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea28000 0 0x5000>;
|
|
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 622>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 622>;
|
|
renesas,fcp = <&fcpvd1>;
|
|
};
|
|
|
|
fcpvb0: fcp@fe96f000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfe96f000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 607>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 607>;
|
|
iommus = <&ipmmu_vp0 5>;
|
|
};
|
|
|
|
fcpvd0: fcp@fea27000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea27000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 603>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 603>;
|
|
iommus = <&ipmmu_vi0 8>;
|
|
};
|
|
|
|
fcpvd1: fcp@fea2f000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea2f000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 602>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 602>;
|
|
iommus = <&ipmmu_vi0 9>;
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a77995";
|
|
reg = <0 0xfeb00000 0 0x80000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 724>,
|
|
<&cpg CPG_MOD 723>;
|
|
clock-names = "du.0", "du.1";
|
|
vsps = <&vspd0 0 &vspd1 0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
du_out_rgb: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_lvds0: endpoint {
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
du_out_lvds1: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu_thermal: cpu-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&thermal>;
|
|
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|