329 lines
9.8 KiB
C
Executable File
329 lines
9.8 KiB
C
Executable File
/*
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* nvt_panel_init.h
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*
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* Created: Mar 22, 2016
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* Copyright: Novatek Inc.
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*
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*/
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#ifndef __NVT_PANEL_INIT_H__
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#define __NVT_PANEL_INIT_H__
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#define TRUE 1
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#define FALSE 0
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#define BLEND_OSD_MODE 0
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#define SEPARATE_OSD_MODE 1
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#define _ENABLE_ 1
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#define _DISABLE_ 0
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#define _DEFAULT_ 0
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#define PANEL_OUTPUT_LVDS_MODE ( 0x80 )
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#define PANEL_OUTPUT_VX1_MODE ( 0x55 )
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#define SYS_MPLL_PAGE_EN *((volatile unsigned long *)(SYS_CLK_REG_BASE + 0xBC))
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#define SYS_CLK_REG_BASE (0xfd020000)
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#define _SYS_MPLL_PAGE_B_EN 0x00000001
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#define _SYS_MPLL_PAGE_0_EN 0x00000002
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#define LCDSEL_SHIFTBITS 2
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#define FHDSEL_SHIFTBITS 1
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#define JEIDASEL_SHIFTBITS 0
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#define HAL_READ_UINT32( _register_, _value_ ) \
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((_value_) = *((volatile unsigned int *)(_register_)))
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#define HAL_WRITE_UINT32( _register_, _value_ ) \
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(*((volatile unsigned int *)(_register_)) = (_value_))
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#define _MPLL_EnablePage0() \
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SYS_MPLL_PAGE_EN = _SYS_MPLL_PAGE_0_EN;
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#define GPE_DIR_OUTPUT(index) ((*(volatile unsigned long*)REG_GPE_DIR) |= (1<<(index)))
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#define GPE_OUTPUT_SET(index) ((*(volatile unsigned long*)REG_GPE_SET) |= (1<<(index)))
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#define REG_GPE_BASE (0xFD100000)
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#define REG_GPE_SET (REG_GPE_BASE+0x04)
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#define REG_GPE_DIR (REG_GPE_BASE+0x08)
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#define GPB_DIR_OUTPUT(index) ((*(volatile unsigned long*)REG_GPB_DIR) |= (1<<(index)))
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#define GPB_OUTPUT_SET(index) ((*(volatile unsigned long*)REG_GPB_SET) |= (1<<(index)))
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#define GPB_OUTPUT_CLEAR(index) ((*(volatile unsigned long*)REG_GPB_CLEAR) = (0x00|(1<<(index))))
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#define GPB_FUN_SET(index) ((*(volatile unsigned long*)REG_GPB_FUN) |= (1<<(index)))
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#define REG_GPB_BASE (0xFD0F0000)
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#define REG_GPB_SET (REG_GPB_BASE+0x44)
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#define REG_GPB_DIR (REG_GPB_BASE+0x48)
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#define REG_GPB_CLEAR (REG_GPB_BASE+0x40)
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#define REG_GPB_FUN (REG_GPB_BASE+0x64)
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#define REG_GPC_BASE (0xFD100000)
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#define REG_GPC_CLEAR (REG_GPC_BASE+0x00)
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#define REG_GPC_SET (REG_GPC_BASE+0x04)
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#define REG_GPC_DIR (REG_GPC_BASE+0x08)
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#define GPC_DIR_OUTPUT(index) ((*(volatile unsigned long*)REG_GPC_DIR) |= (1<<(index)))
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#define GPC_OUTPUT_SET(index) ((*(volatile unsigned long*)REG_GPC_SET) |= (1<<(index)) )
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#define GPC_OUTPUT_CLR(index) ((*(volatile unsigned long*)REG_GPC_CLEAR) |= (1<<(index)) )
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#define P1C0B0X ( 0xFC0B0000 ) // T-Con
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#define P1C0D00 ( 0xFC0D0000 ) // OSD...
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#define P1D0600 ( 0xFD060000 )
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#define P1D1001 ( 0xFD100100 ) // LVDS
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#define P1D100C ( 0xFD100C00 )
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#define P1D1010 ( 0xFD101000 )
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#define P0F ( 0xFE000F00 )
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#define P34 ( 0xFE003400 )
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#define P7F ( 0xFE007F00 )
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#define P1D6A00 ( 0xFD6A0000 )
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#define P1D0200 ( 0xFD020000 )
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#define P1D6800 (0xFD680000)
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#define P1C1E00 (0xFC1E0000)
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#define P1C1E01 (0xFC1E0100)
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#define P1D0600R04 ( P1D0600 + 0x04 )
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#define P1D1001R04 ( P1D1001 + 0x04 )
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#define P1D1001R08 ( P1D1001 + 0x08 )
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#define P1D1001R0C ( P1D1001 + 0x0C )
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#define P1D1001R10 ( P1D1001 + 0x10 )
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#define P1D1001R14 ( P1D1001 + 0x14 )
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#define P1D100CR00 ( P1D100C + 0x00 )
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#define P1D100CR04 ( P1D100C + 0x04 )
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#define P1D100CR08 ( P1D100C + 0x08 )
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#define P1D100CR0C ( P1D100C + 0x0C )
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#define P1D100CR10 ( P1D100C + 0x10 )
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#define P1D1010R1C ( P1D1010 + 0x1C )
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#define P1D100CR18 ( P1D100C + 0x18 )
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#define P1D0200RFC ( P1D0200 + 0xFC )
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#define P0FR00 ( P0F + 0x00 )
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#define P0FR04 ( P0F + 0x04 )
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#define P0FR08 ( P0F + 0x08 )
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#define P0FR0C ( P0F + 0x0C )
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#define P0FR10 ( P0F + 0x10 )
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#define P0FR14 ( P0F + 0x14 )
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#define P0FR18 ( P0F + 0x18 )
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#define P0FR1C ( P0F + 0x1C )
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#define P0FR20 ( P0F + 0x20 )
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#define P0FR28 ( P0F + 0x28 )
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#define P0FR2C ( P0F + 0x2C )
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#define P0FR30 ( P0F + 0x30 )
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#define P0FR34 ( P0F + 0x34 )
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#define P0FR38 ( P0F + 0x38 )
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#define P0FR3C ( P0F + 0x3C )
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#define P0FR40 ( P0F + 0x40 )
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#define P0FR44 ( P0F + 0x44 )
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#define P0FR48 ( P0F + 0x48 )
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#define P0FR5C ( P0F + 0x5C )
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#define P0FR60 ( P0F + 0x60 )
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#define P0FREC ( P0F + 0xEC )
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#define P0FRFC ( P0F + 0xFC )
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#define P1C1E00R00 ( P1C1E00 + 0x00 )
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#define P1C1E01R0C ( P1C1E01 + 0x0C )
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typedef enum _PANEL_SEL
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{
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LED_1366x768,
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LED_1920x1080,
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LED_3840x2160,
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PDP_1920x1080,
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PDP_1024x768,
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PDP_852x480
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}PANEL_SEL;
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typedef enum _EN_DRV_SCLR_VIDEO_OUTPUT_DITHER
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{
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_SCALER_DITHER_10BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_SCALER_DITHER_8BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_SCALER_DITHER_6BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_DP_DITHER_10BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_DP_DITHER_8BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_DP_DITHER_6BITS,
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER_TOTAL
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} EN_DRV_SCLR_VIDEO_OUTPUT_DITHER;
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typedef enum _EN_DRV_SCLR_LVDS_OUT
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{
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EN_DRV_SCLR_LVDS_OUT_SINGLE,
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EN_DRV_SCLR_LVDS_OUT_DUAL,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_1PORT_3PAIR_6X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_1PORT_6PAIR_6X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_2PORT_3PAIR_6X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_1PORT_3PAIR_8X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_1PORT_6PAIR_8X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_2PORT_3PAIR_8X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_2PORT_6PAIR_6X,
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EN_DRV_SCLR_LVDS_OUT_MINI_LVDS_2PORT_6PAIR_8X,
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EN_DRV_SCLR_VX1_OUT_VIDEO_8LAN_OSD_4LAN, // Video 4K2k 60 OSD 4k2k30
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EN_DRV_SCLR_VX1_OUT_VIDEO_8LAN_OSD_2LAN, // Video 4K2k 60 OSD FULL HD
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EN_DRV_SCLR_VX1_OUT_VIDEO_4LAN_OSD_4LAN, // Video 4K2k 30 OSD 4k2k30
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EN_DRV_SCLR_VX1_OUT_VIDEO_4LAN_OSD_2LAN, // Video 4K2k 30 OSD FULL HD
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EN_DRV_SCLR_VX1_OUT_VIDEO_2LAN_OSD_2LAN, // Video FULL HD OSD FULL HD
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EN_DRV_SCLR_LVDS_OUT_TOTAL
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} EN_DRV_SCLR_LVDS_OUT;
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typedef enum _EN_DRV_SCLR_VX1_COMB
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{
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EN_DRV_SCLR_VX1_COMB_1LAN_NOOSD = 0x00, // 74.25MHz Video
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EN_DRV_SCLR_VX1_COMB_1LAN_1LANOSD = 0x01, // 74.25MHz Video / OSD
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EN_DRV_SCLR_VX1_COMB_2LAN_NOOSD = 0x02, // 148.5MHz Video
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EN_DRV_SCLR_VX1_COMB_2LAN_1LANOSD = 0x03, // 148.5MHz Video; 74.25MHz OSD
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EN_DRV_SCLR_VX1_COMB_2LAN_2LANOSD = 0x04, // 148.5MHz Video; 148.5MHz OSD
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EN_DRV_SCLR_VX1_COMB_4LAN_NOOSD = 0x10, // 4K2K30 Video
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EN_DRV_SCLR_VX1_COMB_4LAN_1LANOSD = 0x11, // 4K2K30 Video / 74.25MHz OSD,
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EN_DRV_SCLR_VX1_COMB_4LAN_2LANOSD = 0x12, // 4K2K30 Video / FULL HD OSD,
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EN_DRV_SCLR_VX1_COMB_4LAN_4LANOSD = 0x15, // 4K2K30 Video / 4K2K30 OSD,
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EN_DRV_SCLR_VX1_COMB_8LAN_NOOSD = 0x16, // 4K2K60 Video
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EN_DRV_SCLR_VX1_COMB_8LAN_1LANOSD = 0x17, // 4K2K60 Video / 74.25MHz OSD,
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EN_DRV_SCLR_VX1_COMB_8LAN_2LANOSD = 0x18, // 4K2K60 Video / FULL HD OSD,
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EN_DRV_SCLR_VX1_COMB_8LAN_4LANOSD = 0x1B, // 4K2K60 Video / 4K2K30 OSD,
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EN_DRV_SCLR_VX1_COMB_TOTAL
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} EN_DRV_SCLR_VX1COMB;
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typedef enum _EN_DRV_SCLR_LVDS_FMT
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{
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#if defined(CONFIG_OLD_PANEL_PARAM)
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EN_DRV_SCLR_LVDS_FMT_10BITS_NS,
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EN_DRV_SCLR_LVDS_FMT_10BITS_JEIDA,
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EN_DRV_SCLR_LVDS_FMT_10BITS_VESA,
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EN_DRV_SCLR_LVDS_FMT_8BITS_VESA,
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EN_DRV_SCLR_LVDS_FMT_8BITS_JEIDA,
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#else
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EN_DRV_SCLR_LVDS_FMT_8BITS_JEIDA,
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EN_DRV_SCLR_LVDS_FMT_8BITS_VESA,
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EN_DRV_SCLR_LVDS_FMT_10BITS_JEIDA,
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EN_DRV_SCLR_LVDS_FMT_10BITS_VESA,
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EN_DRV_SCLR_LVDS_FMT_10BITS_NS,
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#endif
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EN_DRV_SCLR_LVDS_FMT_TOTAL
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} EN_DRV_SCLR_LVDS_FMT;
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typedef enum _EN_DRV_SCLR_PANEL_RBSWAP
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{
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EN_DRV_SCLR_PANEL_RBSWAP_NORMAL,
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EN_DRV_SCLR_PANEL_RBSWAP_SWAP,
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EN_DRV_SCLR_PANEL_RBSWAP_TOTAL
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} EN_DRV_SCLR_PANEL_RBSWAP;
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typedef enum _EN_DRV_SCLR_LVDS_ABSWAP
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{
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EN_DRV_SCLR_LVDS_ABSWAP_NORMAL,
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EN_DRV_SCLR_LVDS_ABSWAP_SWAP,
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EN_DRV_SCLR_LVDS_ABSWAP_TOTAL
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} EN_DRV_SCLR_LVDS_ABSWAP;
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typedef enum _EN_DRV_SCLR_LVDS_SINGLE_PORT_SWAP
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{
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EN_DRV_SCLR_LVDS_SINGLE_PORT_SWAP_NORMAL,
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EN_DRV_SCLR_LVDS_SINGLE_PORT_SWAP_SWAP,
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EN_DRV_SCLR_LVDS_SINGLE_PORT_SWAP_TOTAL
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} EN_DRV_SCLR_LVDS_SINGLE_PORT_SWAP;
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struct ST_KER_VID_PANEL_SETTING
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{
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u8 VX1;
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u8 FRC;
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u8 SEP;
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u16 u16Width;
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u16 u16Height;
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u16 u16TypHTotal;
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u8 u8MinHSyncWidth;
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u16 u16MinHSyncBackPorch; // Reserved for future use
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u16 u16HSyncStart;
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u16 u16TypVTotal;
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u16 u16MaxVTotal;
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u8 u8MinVSyncWidth;
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u16 u16MinVSyncBackPorch; // Reserved for future use
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u16 u16VSyncStart;
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u8 u8Phase;
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bool b8DualPixelOutput;
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bool b8ABSwap;
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bool b8ChannelSwap; // Reserved for future use
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bool b8FrameSyncEnable;
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u8 u8FrameSyncMode;
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u8 u8MISC;
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bool b8Mode10Bits;
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bool b8JIEDA;
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bool b8RBSwap;
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u32 u32PLL; // 0.01MHz
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EN_DRV_SCLR_VIDEO_OUTPUT_DITHER eDitheringBit;
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u16 u16LVDSPhase;
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bool DPLL;
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u8 enLvdsFormat;
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u16 PanelPowerOnDelay1;
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u8 u8Tcon;
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u16 u16PanelPowerGPIO;
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u16 u16PanelBackLightGPIO;
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u8 u8PanelType;
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u16 u16VX1SwingG1;
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u16 u16VX1PreEmphasisG1;
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u8 u8LocalDIMControl;
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u8 u8PanelI2cPortNum;
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u8 u8PanelI2cSlaveAddr;
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u16 PanelPowerOnDelay4;
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u8 PanelIOMode;
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};
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struct PST_OSD_DISP_FORMAT
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{
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u32 ulVertical_Start;
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u32 ulHorizontal_Start ;
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u32 ulSrcWidth;
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u32 ulSrcHeight;
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u32 ulDestWidth;
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u32 ulDestHeight;
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u32 ulLineOffset;
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u8 ucColorFormat;
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u8 ucPlaneID;
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u8 ucVFlip_Enable;
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u32* pulBimpAddr;
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};
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typedef enum _EN_DRV_SCLR_GPIO_GROUP
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{
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EN_DRV_SCLR_GPIO_GROUP_A = 0,
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EN_DRV_SCLR_GPIO_GROUP_B = 1,
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EN_DRV_SCLR_GPIO_GROUP_C = 2,
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EN_DRV_SCLR_GPIO_GROUP_D = 3,
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EN_DRV_SCLR_GPIO_GROUP_E = 4,
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EN_DRV_SCLR_GPIO_GROUP_F = 5,
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EN_DRV_SCLR_GPIO_GROUP_G = 6,
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EN_DRV_SCLR_GPIO_GROUP_H = 7,
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EN_DRV_SCLR_GPIO_GROUP_I = 8,
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} EN_DRV_SCLR_GPIO_GROUP;
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u32 UTL_SHL_GetValue( u32 u32Val, u32 u32Msb, u32 u32Lsb );
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u32 UTL_SHL_GetValue( u32 u32Val, u32 u32Msb, u32 u32Lsb );
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void UTL_SHL_WriteClockGenRegMask( u32 u32Addr, u32 u32Msb, u32 u32Lsb, u32 u32Val );
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void _Out_P_SetVx1On(bool bLvdsOn);
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void _Vx1PhyInitSetting( EN_DRV_SCLR_VX1COMB enOutput );
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bool _VID_PowerON_Sequence(void);
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void panel_init_late(void);
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#endif
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