78 lines
2.5 KiB
C
Executable File
78 lines
2.5 KiB
C
Executable File
/**
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NVT pll preset function
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This file will preset PLL value
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@file pll_preset.c
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@ingroup
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@note
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Copyright Novatek Microelectronics Corp. 2016. All rights reserved.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License version 2 as
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published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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static int __init nvt_preset_pll(void)
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{
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struct clk* pll10_clk, *pll0_clk, *pll8_clk, *pll_clk;
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pll10_clk = clk_get(NULL, "pll10");
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if (!IS_ERR(pll10_clk))
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clk_set_rate(pll10_clk, 270000000);
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else
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pr_err("*** %s Get PLL10 Clock error\n", __func__);
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pll0_clk = clk_get(NULL, "pll0");
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if (!IS_ERR(pll0_clk))
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clk_set_rate(pll0_clk, 500000000);
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else
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pr_err("*** %s Get PLL0 Clock error\n", __func__);
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pll8_clk = clk_get(NULL, "pll8");
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if (!IS_ERR(pll8_clk))
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clk_set_rate(pll8_clk, 465000000);
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else
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pr_err("*** %s Get PLL8 Clock error\n", __func__);
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printk("------------------------------\r\n");
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pll10_clk = clk_get(NULL, "pll0");
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pll0_clk = clk_get(NULL, "pll1");
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pll8_clk = clk_get(NULL, "pll13");
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pll_clk = clk_get(NULL, "pll4");
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printk("AXI0=%d AXI1=%d AXI2=%d HCLK=%d\r\n",(int)(clk_get_rate(pll10_clk)+100)/1000000
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,(int)(clk_get_rate(pll0_clk)+100)/1000000
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,(int)(clk_get_rate(pll8_clk)+100)/1000000
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,(int)(clk_get_rate(pll_clk)+100)/1000000);
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pll10_clk = clk_get(NULL, "pll16");
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pll0_clk = clk_get(NULL, "pll3");
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pll8_clk = clk_get(NULL, "pll15");
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pll_clk = clk_get(NULL, "pll14");
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printk("CPU=%d DRAM=%d DSP=%d CODEC=%d\r\n",(int)((clk_get_rate(pll10_clk)+100)/1000000)*8
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,(int)((clk_get_rate(pll0_clk)+100)/1000000)*8
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,(int)((clk_get_rate(pll8_clk)+100)/1000000)
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,(int)(clk_get_rate(pll_clk)+100)/1000000);
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pll10_clk = clk_get(NULL, "pll9");
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pll0_clk = clk_get(NULL, "pll10");
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pll8_clk = clk_get(NULL, "pll11");
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pll_clk = clk_get(NULL, "pll2");
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printk("DISP0=%d DISP1=%d DISP2=%d CNN=%d\r\n",(int)(clk_get_rate(pll10_clk)+100)/1000000
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,(int)(clk_get_rate(pll0_clk)+100)/1000000
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,(int)(clk_get_rate(pll8_clk)+100)/1000000
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,(int)(clk_get_rate(pll_clk)+100)/1000000);
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pll10_clk = clk_get(NULL, "pll8");
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pll0_clk = clk_get(NULL, "pll12");
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printk("MPLL8(VCAP)=%d SSP=%d\r\n",(int)(clk_get_rate(pll10_clk)+100)/1000000
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,(int)(clk_get_rate(pll0_clk)+100)/1000000);
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printk("------------------------------\r\n");
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return 0;
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}
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arch_initcall_sync(nvt_preset_pll);
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