568 lines
15 KiB
ArmAsm
Executable File
568 lines
15 KiB
ArmAsm
Executable File
/*
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* Copyright (C) 2008 The Android Open Source Project
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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#include <machine/cpu-features.h>
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#include <machine/asm.h>
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*/
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#include <features.h>
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#include <endian.h>
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#define PLD(reg, offset) pld [reg, offset]
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#if __ARM_ARCH == 7 || defined(HWCAP_ARM_NEON)
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/* #if 0 */
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.text
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.fpu neon
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.global memcpy
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# .hidden memcpy
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.type memcpy, %function
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.align 4
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/* a prefetch distance of 4 cache-lines works best experimentally */
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#define CACHE_LINE_SIZE 32
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#define PREFETCH_DISTANCE (CACHE_LINE_SIZE*4)
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memcpy:
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.fnstart
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.save {r0, lr}
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/* start preloading as early as possible */
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pld [r1, #(CACHE_LINE_SIZE * 0)]
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stmfd sp!, {r0, lr}
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pld [r1, #(CACHE_LINE_SIZE * 1)]
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/* do we have at least 16-bytes to copy (needed for alignment below) */
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cmp r2, #16
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blo 5f
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/* check if buffers are aligned. If so, run arm-only version */
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eor r3, r0, r1
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ands r3, r3, #0x3
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beq 11f
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/* align destination to cache-line for the write-buffer */
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rsb r3, r0, #0
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ands r3, r3, #0xF
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beq 2f
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/* copy up to 15-bytes (count in r3) */
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sub r2, r2, r3
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movs ip, r3, lsl #31
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ldrmib lr, [r1], #1
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strmib lr, [r0], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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movs ip, r3, lsl #29
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bge 1f
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/* copies 4 bytes, destination 32-bits aligned */
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vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
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vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]!
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1: bcc 2f
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/* copies 8 bytes, destination 64-bits aligned */
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0, :64]!
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2:
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/* preload immediately the next cache line, which we may need */
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pld [r1, #(CACHE_LINE_SIZE * 0)]
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pld [r1, #(CACHE_LINE_SIZE * 1)]
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/* make sure we have at least 64 bytes to copy */
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subs r2, r2, #64
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blo 2f
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/* preload all the cache lines we need. */
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pld [r1, #(CACHE_LINE_SIZE * 2)]
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pld [r1, #(CACHE_LINE_SIZE * 3)]
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1: /* The main loop copies 64 bytes at a time */
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vld1.8 {d0 - d3}, [r1]!
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vld1.8 {d4 - d7}, [r1]!
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pld [r1, #(CACHE_LINE_SIZE * 2)]
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pld [r1, #(CACHE_LINE_SIZE * 3)]
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subs r2, r2, #64
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vst1.8 {d0 - d3}, [r0, :128]!
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vst1.8 {d4 - d7}, [r0, :128]!
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bhs 1b
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2: /* fix-up the remaining count and make sure we have >= 32 bytes left */
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add r2, r2, #64
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subs r2, r2, #32
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blo 4f
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3: /* 32 bytes at a time. These cache lines were already preloaded */
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vld1.8 {d0 - d3}, [r1]!
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subs r2, r2, #32
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vst1.8 {d0 - d3}, [r0, :128]!
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bhs 3b
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4: /* less than 32 left */
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add r2, r2, #32
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tst r2, #0x10
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beq 5f
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/* copies 16 bytes, 128-bits aligned */
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vld1.8 {d0, d1}, [r1]!
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vst1.8 {d0, d1}, [r0, :128]!
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5: /* copy up to 15-bytes (count in r2) */
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movs ip, r2, lsl #29
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bcc 1f
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [r0]!
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1: bge 2f
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vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
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vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]!
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2: movs ip, r2, lsl #31
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ldrmib r3, [r1], #1
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ldrcsb ip, [r1], #1
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ldrcsb lr, [r1], #1
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strmib r3, [r0], #1
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strcsb ip, [r0], #1
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strcsb lr, [r0], #1
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ldmfd sp!, {r0, lr}
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bx lr
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11:
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/* Simple arm-only copy loop to handle aligned copy operations */
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stmfd sp!, {r4, r5, r6, r7, r8}
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pld [r1, #(CACHE_LINE_SIZE * 2)]
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/* Check alignment */
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rsb r3, r1, #0
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ands r3, #3
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beq 2f
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/* align source to 32 bits. We need to insert 2 instructions between
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* a ldr[b|h] and str[b|h] because byte and half-word instructions
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* stall 2 cycles.
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*/
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movs r12, r3, lsl #31
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sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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ldrmib r3, [r1], #1
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ldrcsb r4, [r1], #1
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ldrcsb r5, [r1], #1
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strmib r3, [r0], #1
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strcsb r4, [r0], #1
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strcsb r5, [r0], #1
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2:
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subs r2, #32
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blt 5f
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pld [r1, #(CACHE_LINE_SIZE * 3)]
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3: /* Main copy loop, copying 32 bytes at a time */
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pld [r1, #(CACHE_LINE_SIZE * 4)]
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ldmia r1!, {r3, r4, r5, r6, r7, r8, r12, lr}
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subs r2, r2, #32
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stmia r0!, {r3, r4, r5, r6, r7, r8, r12, lr}
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bge 3b
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5: /* Handle any remaining bytes */
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adds r2, #32
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beq 6f
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movs r12, r2, lsl #28
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ldmcsia r1!, {r3, r4, r5, r6} /* 16 bytes */
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ldmmiia r1!, {r7, r8} /* 8 bytes */
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stmcsia r0!, {r3, r4, r5, r6}
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stmmiia r0!, {r7, r8}
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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ldrmih r4, [r1], #2 /* 2 bytes */
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strcs r3, [r0], #4
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strmih r4, [r0], #2
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tst r2, #0x1
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ldrneb r3, [r1] /* last byte */
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strneb r3, [r0]
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6:
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ldmfd sp!, {r4, r5, r6, r7, r8}
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ldmfd sp!, {r0, pc}
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#else /* __ARM_ARCH__ < 7 */
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/*
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* Optimized memcpy() for ARM.
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*
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* note that memcpy() always returns the destination pointer,
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* so we have to preserve R0.
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*/
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.global memcpy
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.type memcpy, %function
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# .align 4
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memcpy:
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/*
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* The stack must always be 64-bits aligned to be compliant with the
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* ARM ABI. Since we have to save R0, we might as well save R4
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* which we can use for better pipelining of the reads below
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*/
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# .save {r0, r4, lr}
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stmfd sp!, {r0, r4, lr}
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/* Making room for r5-r11 which will be spilled later */
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# .pad #28
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sub sp, sp, #28
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/* preload the destination because we'll align it to a cache line */
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/* with small writes. Also start the source "pump". */
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PLD (r0, #0)
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PLD (r1, #0)
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PLD (r1, #32)
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/* it simplifies things to take care of len<4 early */
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cmp r2, #4
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blo copy_last_3_and_return
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/*
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* compute the offset to align the source
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* offset = (4-(src&3))&3 = -src & 3
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*/
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rsb r3, r1, #0
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ands r3, r3, #3
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beq src_aligned
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/*
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* align source to 32 bits. We need to insert 2 instructions between
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* a ldr[b|h] and str[b|h] because byte and half-word instructions
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* stall 2 cycles.
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*/
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movs r12, r3, lsl #31
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sub r2, r2, r3 /* we know that r3 <= r2 because r2 >= 4 */
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ldrmib r3, [r1], #1
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ldrcsb r4, [r1], #1
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ldrcsb r12,[r1], #1
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strmib r3, [r0], #1
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strcsb r4, [r0], #1
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strcsb r12,[r0], #1
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src_aligned:
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/* see if src and dst are aligned together (congruent) */
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eor r12, r0, r1
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tst r12, #3
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bne non_congruent
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* align the destination to a cache-line */
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rsb r3, r0, #0
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ands r3, r3, #0x1C
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beq congruent_aligned32
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cmp r3, r2
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andhi r3, r2, #0x1C
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/* conditionnaly copies 0 to 7 words (length in r3) */
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movs r12, r3, lsl #28
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ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmiia r1!, {r8, r9} /* 8 bytes */
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stmcsia r0!, {r4, r5, r6, r7}
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stmmiia r0!, {r8, r9}
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tst r3, #0x4
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ldrne r10,[r1], #4 /* 4 bytes */
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strne r10,[r0], #4
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sub r2, r2, r3
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congruent_aligned32:
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/*
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* here source is aligned to 32 bytes.
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*/
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cached_aligned32:
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subs r2, r2, #32
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blo less_than_32_left
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/*
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* We preload a cache-line up to 64 bytes ahead. On the 926, this will
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* stall only until the requested world is fetched, but the linefill
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* continues in the the background.
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* While the linefill is going, we write our previous cache-line
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* into the write-buffer (which should have some free space).
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* When the linefill is done, the writebuffer will
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* start dumping its content into memory
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*
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* While all this is going, we then load a full cache line into
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* 8 registers, this cache line should be in the cache by now
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* (or partly in the cache).
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*
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* This code should work well regardless of the source/dest alignment.
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*
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*/
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/* Align the preload register to a cache-line because the cpu does */
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/* "critical word first" (the first word requested is loaded first). */
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bic r12, r1, #0x1F
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add r12, r12, #64
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1: ldmia r1!, { r4-r11 }
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PLD (r12, #64)
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subs r2, r2, #32
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/* NOTE: if r12 is more than 64 ahead of r1, the following ldrhi
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* for ARM9 preload will not be safely guarded by the preceding subs.
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* When it is safely guarded the only possibility to have SIGSEGV here
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* is because the caller overstates the length.
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*/
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ldrhi r3, [r12], #32 /* cheap ARM9 preload */
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stmia r0!, { r4-r11 }
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bhs 1b
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add r2, r2, #32
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less_than_32_left:
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/*
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* less than 32 bytes left at this point (length in r2)
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*/
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/* skip all this if there is nothing to do, which should
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* be a common case (if not executed the code below takes
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* about 16 cycles)
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*/
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tst r2, #0x1F
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beq 1f
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/* conditionnaly copies 0 to 31 bytes */
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movs r12, r2, lsl #28
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ldmcsia r1!, {r4, r5, r6, r7} /* 16 bytes */
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ldmmiia r1!, {r8, r9} /* 8 bytes */
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stmcsia r0!, {r4, r5, r6, r7}
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stmmiia r0!, {r8, r9}
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movs r12, r2, lsl #30
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ldrcs r3, [r1], #4 /* 4 bytes */
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ldrmih r4, [r1], #2 /* 2 bytes */
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strcs r3, [r0], #4
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strmih r4, [r0], #2
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tst r2, #0x1
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ldrneb r3, [r1] /* last byte */
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strneb r3, [r0]
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/* we're done! restore everything and return */
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1: ldmfd sp!, {r5-r11}
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ldmfd sp!, {r0, r4, lr}
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bx lr
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/********************************************************************/
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non_congruent:
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/*
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* here source is aligned to 4 bytes
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* but destination is not.
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*
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* in the code below r2 is the number of bytes read
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* (the number of bytes written is always smaller, because we have
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* partial words in the shift queue)
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*/
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cmp r2, #4
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blo copy_last_3_and_return
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/* Use post-incriment mode for stm to spill r5-r11 to reserved stack
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* frame. Don't update sp.
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*/
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stmea sp, {r5-r11}
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/* compute shifts needed to align src to dest */
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rsb r5, r0, #0
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and r5, r5, #3 /* r5 = # bytes in partial words */
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mov r12, r5, lsl #3 /* r12 = right */
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rsb lr, r12, #32 /* lr = left */
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/* read the first word */
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ldr r3, [r1], #4
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sub r2, r2, #4
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/* write a partial word (0 to 3 bytes), such that destination
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* becomes aligned to 32 bits (r5 = nb of words to copy for alignment)
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*/
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movs r5, r5, lsl #31
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strmib r3, [r0], #1
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movmi r3, r3, lsr #8
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strcsb r3, [r0], #1
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movcs r3, r3, lsr #8
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strcsb r3, [r0], #1
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movcs r3, r3, lsr #8
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cmp r2, #4
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blo partial_word_tail
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/* Align destination to 32 bytes (cache line boundary) */
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1: tst r0, #0x1c
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beq 2f
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ldr r5, [r1], #4
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sub r2, r2, #4
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orr r4, r3, r5, lsl lr
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mov r3, r5, lsr r12
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str r4, [r0], #4
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cmp r2, #4
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bhs 1b
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blo partial_word_tail
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/* copy 32 bytes at a time */
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2: subs r2, r2, #32
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blo less_than_thirtytwo
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/* Use immediate mode for the shifts, because there is an extra cycle
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* for register shifts, which could account for up to 50% of
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* performance hit.
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*/
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cmp r12, #24
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beq loop24
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cmp r12, #8
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beq loop8
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loop16:
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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PLD (r1, #64)
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subs r2, r2, #32
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ldrhs r12, [r1], #4
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orr r3, r3, r4, lsl #16
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mov r4, r4, lsr #16
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orr r4, r4, r5, lsl #16
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mov r5, r5, lsr #16
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orr r5, r5, r6, lsl #16
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mov r6, r6, lsr #16
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orr r6, r6, r7, lsl #16
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mov r7, r7, lsr #16
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orr r7, r7, r8, lsl #16
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mov r8, r8, lsr #16
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orr r8, r8, r9, lsl #16
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mov r9, r9, lsr #16
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orr r9, r9, r10, lsl #16
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mov r10, r10, lsr #16
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orr r10, r10, r11, lsl #16
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stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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mov r3, r11, lsr #16
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bhs 1b
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b less_than_thirtytwo
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loop8:
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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PLD (r1, #64)
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subs r2, r2, #32
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ldrhs r12, [r1], #4
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orr r3, r3, r4, lsl #24
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mov r4, r4, lsr #8
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orr r4, r4, r5, lsl #24
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mov r5, r5, lsr #8
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orr r5, r5, r6, lsl #24
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mov r6, r6, lsr #8
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orr r6, r6, r7, lsl #24
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mov r7, r7, lsr #8
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orr r7, r7, r8, lsl #24
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mov r8, r8, lsr #8
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orr r8, r8, r9, lsl #24
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mov r9, r9, lsr #8
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orr r9, r9, r10, lsl #24
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|
mov r10, r10, lsr #8
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orr r10, r10, r11, lsl #24
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stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
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mov r3, r11, lsr #8
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bhs 1b
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b less_than_thirtytwo
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|
|
|
loop24:
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ldr r12, [r1], #4
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1: mov r4, r12
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ldmia r1!, { r5,r6,r7, r8,r9,r10,r11}
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|
PLD (r1, #64)
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subs r2, r2, #32
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|
ldrhs r12, [r1], #4
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|
orr r3, r3, r4, lsl #8
|
|
mov r4, r4, lsr #24
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|
orr r4, r4, r5, lsl #8
|
|
mov r5, r5, lsr #24
|
|
orr r5, r5, r6, lsl #8
|
|
mov r6, r6, lsr #24
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|
orr r6, r6, r7, lsl #8
|
|
mov r7, r7, lsr #24
|
|
orr r7, r7, r8, lsl #8
|
|
mov r8, r8, lsr #24
|
|
orr r8, r8, r9, lsl #8
|
|
mov r9, r9, lsr #24
|
|
orr r9, r9, r10, lsl #8
|
|
mov r10, r10, lsr #24
|
|
orr r10, r10, r11, lsl #8
|
|
stmia r0!, {r3,r4,r5,r6, r7,r8,r9,r10}
|
|
mov r3, r11, lsr #24
|
|
bhs 1b
|
|
|
|
|
|
less_than_thirtytwo:
|
|
/* copy the last 0 to 31 bytes of the source */
|
|
rsb r12, lr, #32 /* we corrupted r12, recompute it */
|
|
add r2, r2, #32
|
|
cmp r2, #4
|
|
blo partial_word_tail
|
|
|
|
1: ldr r5, [r1], #4
|
|
sub r2, r2, #4
|
|
orr r4, r3, r5, lsl lr
|
|
mov r3, r5, lsr r12
|
|
str r4, [r0], #4
|
|
cmp r2, #4
|
|
bhs 1b
|
|
|
|
partial_word_tail:
|
|
/* we have a partial word in the input buffer */
|
|
movs r5, lr, lsl #(31-3)
|
|
strmib r3, [r0], #1
|
|
movmi r3, r3, lsr #8
|
|
strcsb r3, [r0], #1
|
|
movcs r3, r3, lsr #8
|
|
strcsb r3, [r0], #1
|
|
|
|
/* Refill spilled registers from the stack. Don't update sp. */
|
|
ldmfd sp, {r5-r11}
|
|
|
|
copy_last_3_and_return:
|
|
movs r2, r2, lsl #31 /* copy remaining 0, 1, 2 or 3 bytes */
|
|
ldrmib r2, [r1], #1
|
|
ldrcsb r3, [r1], #1
|
|
ldrcsb r12,[r1]
|
|
strmib r2, [r0], #1
|
|
strcsb r3, [r0], #1
|
|
strcsb r12,[r0]
|
|
|
|
/* we're done! restore sp and spilled registers and return */
|
|
add sp, sp, #28
|
|
ldmfd sp!, {r0, r4, lr}
|
|
bx lr
|
|
|
|
#endif /* __ARM_ARCH__ < 7 */
|
|
.size memcpy, .-memcpy
|