356 lines
13 KiB
C
Executable File
356 lines
13 KiB
C
Executable File
/*
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* Include file private to the SOC Interconnect support files.
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*
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* Copyright (C) 1999-2019, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: siutils_priv.h 795345 2018-12-18 16:52:03Z $
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*/
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#ifndef _siutils_priv_h_
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#define _siutils_priv_h_
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#if defined(SI_ERROR_ENFORCE)
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#define SI_ERROR(args) printf args
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#else
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#define SI_ERROR(args)
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#endif // endif
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#if defined(ENABLE_CORECAPTURE)
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#define SI_PRINT(args) osl_wificc_logDebug args
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#else
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#define SI_PRINT(args) printf args
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#endif /* ENABLE_CORECAPTURE */
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#define SI_MSG(args)
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#ifdef BCMDBG_SI
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#define SI_VMSG(args) printf args
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#else
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#define SI_VMSG(args)
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#endif // endif
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#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
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typedef uint32 (*si_intrsoff_t)(void *intr_arg);
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typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
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typedef bool (*si_intrsenabled_t)(void *intr_arg);
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#define SI_GPIO_MAX 16
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typedef struct gci_gpio_item {
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void *arg;
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uint8 gci_gpio;
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uint8 status;
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gci_gpio_handler_t handler;
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struct gci_gpio_item *next;
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} gci_gpio_item_t;
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#define AI_SLAVE_WRAPPER 0
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#define AI_MASTER_WRAPPER 1
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typedef struct axi_wrapper {
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uint32 mfg;
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uint32 cid;
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uint32 rev;
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uint32 wrapper_type;
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uint32 wrapper_addr;
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uint32 wrapper_size;
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} axi_wrapper_t;
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#define SI_MAX_AXI_WRAPPERS 32
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#define AI_REG_READ_TIMEOUT 300 /* in msec */
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/* for some combo chips, BT side accesses chipcommon->0x190, as a 16 byte addr */
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/* register at 0x19C doesn't exist, so error is logged at the slave wrapper */
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#define BT_CC_SPROM_BADREG_LO 0x18000190
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#define BT_CC_SPROM_BADREG_SIZE 4
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#define BT_CC_SPROM_BADREG_HI 0
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#define BCM4350_BT_AXI_ID 6
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#define BCM4345_BT_AXI_ID 6
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#define BCM4349_BT_AXI_ID 5
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#define BCM4364_BT_AXI_ID 5
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/* for BT logging and memory dump, ignore failed access to BT memory */
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#define BCM4347_BT_ADDR_HI 0
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#define BCM4347_BT_ADDR_LO 0x19000000 /* BT address space */
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#define BCM4347_BT_SIZE 0x01000000 /* BT address space size */
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#define BCM4347_UNUSED_AXI_ID 0xffffffff
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#define BCM4347_CC_AXI_ID 0
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#define BCM4347_PCIE_AXI_ID 1
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typedef struct si_cores_info {
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volatile void *regs[SI_MAXCORES]; /* other regs va */
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uint coreid[SI_MAXCORES]; /**< id of each core */
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uint32 coresba[SI_MAXCORES]; /**< backplane address of each core */
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void *regs2[SI_MAXCORES]; /**< va of each core second register set (usbh20) */
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uint32 coresba2[SI_MAXCORES]; /**< address of each core second register set (usbh20) */
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uint32 coresba_size[SI_MAXCORES]; /**< backplane address space size */
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uint32 coresba2_size[SI_MAXCORES]; /**< second address space size */
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void *wrappers[SI_MAXCORES]; /**< other cores wrapper va */
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uint32 wrapba[SI_MAXCORES]; /**< address of controlling wrapper */
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void *wrappers2[SI_MAXCORES]; /**< other cores wrapper va */
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uint32 wrapba2[SI_MAXCORES]; /**< address of controlling wrapper */
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void *wrappers3[SI_MAXCORES]; /**< other cores wrapper va */
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uint32 wrapba3[SI_MAXCORES]; /**< address of controlling wrapper */
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uint32 cia[SI_MAXCORES]; /**< erom cia entry for each core */
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uint32 cib[SI_MAXCORES]; /**< erom cia entry for each core */
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uint32 csp2ba[SI_MAXCORES]; /**< Second slave port base addr 0 */
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uint32 csp2ba_size[SI_MAXCORES]; /**< Second slave port addr space size */
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} si_cores_info_t;
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/** misc si info needed by some of the routines */
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typedef struct si_info {
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struct si_pub pub; /**< back plane public state (must be first field) */
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void *osh; /**< osl os handle */
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void *sdh; /**< bcmsdh handle */
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uint dev_coreid; /**< the core provides driver functions */
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void *intr_arg; /**< interrupt callback function arg */
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si_intrsoff_t intrsoff_fn; /**< turns chip interrupts off */
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si_intrsrestore_t intrsrestore_fn; /**< restore chip interrupts */
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si_intrsenabled_t intrsenabled_fn; /**< check if interrupts are enabled */
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void *pch; /**< PCI/E core handle */
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bool memseg; /**< flag to toggle MEM_SEG register */
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char *vars;
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uint varsz;
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volatile void *curmap; /* current regs va */
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uint curidx; /**< current core index */
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uint numcores; /**< # discovered cores */
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void *curwrap; /**< current wrapper va */
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uint32 oob_router; /**< oob router registers for axi */
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uint32 oob_router1; /**< oob router registers for axi */
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si_cores_info_t *cores_info;
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gci_gpio_item_t *gci_gpio_head; /**< gci gpio interrupts head */
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uint chipnew; /**< new chip number */
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uint second_bar0win; /**< Backplane region */
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uint num_br; /**< # discovered bridges */
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uint32 br_wrapba[SI_MAXBR]; /**< address of bridge controlling wrapper */
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uint32 xtalfreq;
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uint32 openloop_dco_code; /**< OPEN loop calibration dco code */
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uint8 spurmode;
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bool device_removed;
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uint axi_num_wrappers;
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axi_wrapper_t * axi_wrapper;
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uint8 device_wake_opt; /* device_wake GPIO number */
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uint8 lhl_ps_mode;
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} si_info_t;
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#define SI_INFO(sih) ((si_info_t *)(uintptr)sih)
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#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
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ISALIGNED((x), SI_CORE_SIZE))
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#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
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#define BADCOREADDR 0
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#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
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#define NOREV -1 /**< Invalid rev */
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#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
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((si)->pub.buscoretype == PCI_CORE_ID))
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#define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
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((si)->pub.buscoretype == PCIE_CORE_ID))
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#define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
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((si)->pub.buscoretype == PCIE2_CORE_ID))
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#define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si))
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#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
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/** Newer chips can access PCI/PCIE and CC core without requiring to change PCI BAR0 WIN */
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#define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
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#define CCREGS_FAST(si) \
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(((si)->curmap == NULL) ? NULL : \
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((volatile char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
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#define PCIEREGS(si) (((volatile char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
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/*
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* Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
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* after core switching to avoid invalid register accesss inside ISR.
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*/
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#define INTR_OFF(si, intr_val) \
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if ((si)->intrsoff_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
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intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
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#define INTR_RESTORE(si, intr_val) \
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if ((si)->intrsrestore_fn && (si)->cores_info->coreid[(si)->curidx] == (si)->dev_coreid) { \
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(*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
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/* dynamic clock control defines */
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#define LPOMINFREQ 25000 /**< low power oscillator min */
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#define LPOMAXFREQ 43000 /**< low power oscillator max */
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#define XTALMINFREQ 19800000 /**< 20 MHz - 1% */
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#define XTALMAXFREQ 20200000 /**< 20 MHz + 1% */
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#define PCIMINFREQ 25000000 /**< 25 MHz */
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#define PCIMAXFREQ 34000000 /**< 33 MHz + fudge */
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#define ILP_DIV_5MHZ 0 /**< ILP = 5 MHz */
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#define ILP_DIV_1MHZ 4 /**< ILP = 1 MHz */
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/* GPIO Based LED powersave defines */
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#define DEFAULT_GPIO_ONTIME 10 /**< Default: 10% on */
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#define DEFAULT_GPIO_OFFTIME 90 /**< Default: 10% on */
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#ifndef DEFAULT_GPIOTIMERVAL
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#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
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#endif // endif
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/* Silicon Backplane externs */
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extern void sb_scan(si_t *sih, volatile void *regs, uint devid);
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extern uint sb_coreid(si_t *sih);
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extern uint sb_intflag(si_t *sih);
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extern uint sb_flag(si_t *sih);
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extern void sb_setint(si_t *sih, int siflag);
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extern uint sb_corevendor(si_t *sih);
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extern uint sb_corerev(si_t *sih);
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extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
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extern volatile uint32 *sb_corereg_addr(si_t *sih, uint coreidx, uint regoff);
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extern bool sb_iscoreup(si_t *sih);
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extern volatile void *sb_setcoreidx(si_t *sih, uint coreidx);
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extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
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extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
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extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
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extern void sb_commit(si_t *sih);
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extern uint32 sb_base(uint32 admatch);
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extern uint32 sb_size(uint32 admatch);
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extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
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extern void sb_core_disable(si_t *sih, uint32 bits);
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extern uint32 sb_addrspace(si_t *sih, uint asidx);
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extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
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extern int sb_numaddrspaces(si_t *sih);
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extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
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extern bool sb_taclear(si_t *sih, bool details);
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#if defined(BCMDBG_PHYDUMP)
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extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
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#endif // endif
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/* Wake-on-wireless-LAN (WOWL) */
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extern bool sb_pci_pmecap(si_t *sih);
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struct osl_info;
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extern bool sb_pci_fastpmecap(struct osl_info *osh);
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extern bool sb_pci_pmeclr(si_t *sih);
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extern void sb_pci_pmeen(si_t *sih);
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extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
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/* AMBA Interconnect exported externs */
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extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
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void *sdh, char **vars, uint *varsz);
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extern si_t *ai_kattach(osl_t *osh);
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extern void ai_scan(si_t *sih, void *regs, uint devid);
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extern uint ai_flag(si_t *sih);
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extern uint ai_flag_alt(si_t *sih);
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extern void ai_setint(si_t *sih, int siflag);
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extern uint ai_coreidx(si_t *sih);
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extern uint ai_corevendor(si_t *sih);
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extern uint ai_corerev(si_t *sih);
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extern uint ai_corerev_minor(si_t *sih);
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extern volatile uint32 *ai_corereg_addr(si_t *sih, uint coreidx, uint regoff);
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extern bool ai_iscoreup(si_t *sih);
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extern volatile void *ai_setcoreidx(si_t *sih, uint coreidx);
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extern volatile void *ai_setcoreidx_2ndwrap(si_t *sih, uint coreidx);
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extern volatile void *ai_setcoreidx_3rdwrap(si_t *sih, uint coreidx);
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extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
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extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
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extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
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extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
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extern uint ai_corereg_writeonly(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
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extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
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extern void ai_d11rsdb_core_reset(si_t *sih, uint32 bits,
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uint32 resetbits, void *p, volatile void *s);
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extern void ai_core_disable(si_t *sih, uint32 bits);
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extern void ai_d11rsdb_core_disable(const si_info_t *sii, uint32 bits,
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aidmp_t *pmacai, aidmp_t *smacai);
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extern int ai_numaddrspaces(si_t *sih);
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extern uint32 ai_addrspace(si_t *sih, uint spidx, uint baidx);
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extern uint32 ai_addrspacesize(si_t *sih, uint spidx, uint baidx);
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extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
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extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
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extern void ai_update_backplane_timeouts(si_t *sih, bool enable, uint32 timeout, uint32 cid);
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extern uint32 ai_clear_backplane_to(si_t *sih);
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void ai_force_clocks(si_t *sih, uint clock_state);
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extern uint ai_num_slaveports(si_t *sih, uint coreidx);
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#ifdef BCM_BACKPLANE_TIMEOUT
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uint32 ai_clear_backplane_to_fast(si_t *sih, void * addr);
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#endif /* BCM_BACKPLANE_TIMEOUT */
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#if defined(AXI_TIMEOUTS) || defined(BCM_BACKPLANE_TIMEOUT)
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extern uint32 ai_clear_backplane_to_per_core(si_t *sih, uint coreid, uint coreunit, void * wrap);
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#endif /* AXI_TIMEOUTS || BCM_BACKPLANE_TIMEOUT */
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#if defined(BCMDBG_PHYDUMP)
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extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
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#endif // endif
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extern uint32 ai_wrapper_dump_buf_size(si_t *sih);
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extern uint32 ai_wrapper_dump_binary(si_t *sih, uchar *p);
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extern bool ai_check_enable_backplane_log(si_t *sih);
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extern uint32 ai_wrapper_dump_last_timeout(si_t *sih, uint32 *error, uint32 *core, uint32 *ba,
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uchar *p);
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#define ub_scan(a, b, c) do {} while (0)
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#define ub_flag(a) (0)
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#define ub_setint(a, b) do {} while (0)
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#define ub_coreidx(a) (0)
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#define ub_corevendor(a) (0)
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#define ub_corerev(a) (0)
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#define ub_iscoreup(a) (0)
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#define ub_setcoreidx(a, b) (0)
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#define ub_core_cflags(a, b, c) (0)
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#define ub_core_cflags_wo(a, b, c) do {} while (0)
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#define ub_core_sflags(a, b, c) (0)
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#define ub_corereg(a, b, c, d, e) (0)
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#define ub_core_reset(a, b, c) do {} while (0)
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#define ub_core_disable(a, b) do {} while (0)
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#define ub_numaddrspaces(a) (0)
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#define ub_addrspace(a, b) (0)
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#define ub_addrspacesize(a, b) (0)
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#define ub_view(a, b) do {} while (0)
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#define ub_dumpregs(a, b) do {} while (0)
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#endif /* _siutils_priv_h_ */
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