431 lines
23 KiB
C
Executable File
431 lines
23 KiB
C
Executable File
/**
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PAD controller header
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PAD controller header
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@file pad.h
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@ingroup mIDrvSys_PAD
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@note Nothing
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Copyright Novatek Microelectronics Corp. 2012. All rights reserved.
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*/
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#ifndef _PAD_H
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#define _PAD_H
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#include <kwrap/nvt_type.h>
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/**
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@addtogroup mIDrvSys_PAD
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*/
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//@{
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#define PAD_C_GPIO_BASE 0
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#define PAD_S_GPIO_BASE 96
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#define PAD_P_GPIO_BASE 128
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#define PAD_L_GPIO_BASE 224
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#define PAD_DSI_GPIO_BASE 256
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#define PAD_D_GPIO_BASE 288
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#define PAD_H_GPIO_BASE 320
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#define PAD_A_GPIO_BASE 352
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#define PAD_DS_DSI_GPIO_BASE 384
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#define PAD_DS_GROUP_10 0x00000000
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#define PAD_DS_GROUP_16 0x10000000
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#define PAD_DS_GROUP_40 0x80000000
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#define PAD_DS_GROUP_MASK 0xF0000000
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/**
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@name Pad type pin ID.
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Pad type pin ID.
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Pad ID of pad_set_pull_updown (), pad_get_pull_updown ().
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*/
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#define PAD_PIN_NOT_EXIST (64) // For backward compatible
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//@{
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typedef enum {
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//C_GPIO group
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PAD_PIN_CGPIO0 = (PAD_C_GPIO_BASE + 0), ///< C_GPIO_0
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PAD_PIN_CGPIO1 = (PAD_C_GPIO_BASE + 2), ///< C_GPIO_1
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PAD_PIN_CGPIO2 = (PAD_C_GPIO_BASE + 4), ///< C_GPIO_2
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PAD_PIN_CGPIO3 = (PAD_C_GPIO_BASE + 6), ///< C_GPIO_3
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PAD_PIN_CGPIO4 = (PAD_C_GPIO_BASE + 8), ///< C_GPIO_4
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PAD_PIN_CGPIO5 = (PAD_C_GPIO_BASE + 10), ///< C_GPIO_5
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PAD_PIN_CGPIO6 = (PAD_C_GPIO_BASE + 12), ///< C_GPIO_6
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PAD_PIN_CGPIO7 = (PAD_C_GPIO_BASE + 14), ///< C_GPIO_7
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PAD_PIN_CGPIO8 = (PAD_C_GPIO_BASE + 16), ///< C_GPIO_8
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PAD_PIN_CGPIO9 = (PAD_C_GPIO_BASE + 18), ///< C_GPIO_9
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PAD_PIN_CGPIO10 = (PAD_C_GPIO_BASE + 20), ///< C_GPIO_10
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PAD_PIN_CGPIO11 = (PAD_C_GPIO_BASE + 22), ///< C_GPIO_11
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PAD_PIN_CGPIO12 = (PAD_C_GPIO_BASE + 24), ///< C_GPIO_12
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PAD_PIN_CGPIO13 = (PAD_C_GPIO_BASE + 26), ///< C_GPIO_13
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PAD_PIN_CGPIO14 = (PAD_C_GPIO_BASE + 28), ///< C_GPIO_14
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PAD_PIN_CGPIO15 = (PAD_C_GPIO_BASE + 30), ///< C_GPIO_15
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PAD_PIN_CGPIO16 = (PAD_C_GPIO_BASE + 32), ///< C_GPIO_16
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PAD_PIN_CGPIO17 = (PAD_C_GPIO_BASE + 34), ///< C_GPIO_17
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PAD_PIN_CGPIO18 = (PAD_C_GPIO_BASE + 36), ///< C_GPIO_18
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PAD_PIN_CGPIO19 = (PAD_C_GPIO_BASE + 38), ///< C_GPIO_19
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PAD_PIN_CGPIO20 = (PAD_C_GPIO_BASE + 40), ///< C_GPIO_20
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PAD_PIN_CGPIO21 = (PAD_C_GPIO_BASE + 42), ///< C_GPIO_21
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PAD_PIN_CGPIO22 = (PAD_C_GPIO_BASE + 44), ///< C_GPIO_22
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//S_GPIO group
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PAD_PIN_SGPIO0 = (PAD_S_GPIO_BASE + 0), ///< S_GPIO_0
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PAD_PIN_SGPIO1 = (PAD_S_GPIO_BASE + 2), ///< S_GPIO_1
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PAD_PIN_SGPIO2 = (PAD_S_GPIO_BASE + 4), ///< S_GPIO_2
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PAD_PIN_SGPIO3 = (PAD_S_GPIO_BASE + 6), ///< S_GPIO_3
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PAD_PIN_SGPIO4 = (PAD_S_GPIO_BASE + 8), ///< S_GPIO_4
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PAD_PIN_SGPIO5 = (PAD_S_GPIO_BASE + 10), ///< S_GPIO_5
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PAD_PIN_SGPIO6 = (PAD_S_GPIO_BASE + 12), ///< S_GPIO_6
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PAD_PIN_SGPIO7 = (PAD_S_GPIO_BASE + 14), ///< S_GPIO_7
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PAD_PIN_SGPIO8 = (PAD_S_GPIO_BASE + 16), ///< S_GPIO_8
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PAD_PIN_SGPIO9 = (PAD_S_GPIO_BASE + 18), ///< S_GPIO_9 ///< Package not support
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PAD_PIN_SGPIO10 = (PAD_S_GPIO_BASE + 20), ///< S_GPIO_10 ///< Package not support
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PAD_PIN_SGPIO11 = (PAD_S_GPIO_BASE + 22), ///< S_GPIO_11 ///< Package not support
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PAD_PIN_SGPIO12 = (PAD_S_GPIO_BASE + 24), ///< S_GPIO_12 ///< Package not support
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//P_GPIO group
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PAD_PIN_PGPIO0 = (PAD_P_GPIO_BASE + 0), ///< P_GPIO_0
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PAD_PIN_PGPIO1 = (PAD_P_GPIO_BASE + 2), ///< P_GPIO_1
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PAD_PIN_PGPIO2 = (PAD_P_GPIO_BASE + 4), ///< P_GPIO_2
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PAD_PIN_PGPIO3 = (PAD_P_GPIO_BASE + 6), ///< P_GPIO_3
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PAD_PIN_PGPIO4 = (PAD_P_GPIO_BASE + 8), ///< P_GPIO_4
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PAD_PIN_PGPIO5 = (PAD_P_GPIO_BASE + 10), ///< P_GPIO_5
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PAD_PIN_PGPIO6 = (PAD_P_GPIO_BASE + 12), ///< P_GPIO_6
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PAD_PIN_PGPIO7 = (PAD_P_GPIO_BASE + 14), ///< P_GPIO_7
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PAD_PIN_PGPIO8 = (PAD_P_GPIO_BASE + 16), ///< P_GPIO_8
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PAD_PIN_PGPIO9 = (PAD_P_GPIO_BASE + 18), ///< P_GPIO_9
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PAD_PIN_PGPIO10 = (PAD_P_GPIO_BASE + 20), ///< P_GPIO_10
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PAD_PIN_PGPIO11 = (PAD_P_GPIO_BASE + 22), ///< P_GPIO_11
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PAD_PIN_PGPIO12 = (PAD_P_GPIO_BASE + 24), ///< P_GPIO_12
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PAD_PIN_PGPIO13 = (PAD_P_GPIO_BASE + 26), ///< P_GPIO_13 ///< Package not support
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PAD_PIN_PGPIO14 = (PAD_P_GPIO_BASE + 28), ///< P_GPIO_14 ///< Package not support
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PAD_PIN_PGPIO15 = (PAD_P_GPIO_BASE + 30), ///< P_GPIO_15 ///< Package not support
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PAD_PIN_PGPIO16 = (PAD_P_GPIO_BASE + 32), ///< P_GPIO_16 ///< Package not support
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PAD_PIN_PGPIO17 = (PAD_P_GPIO_BASE + 34), ///< P_GPIO_17
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PAD_PIN_PGPIO18 = (PAD_P_GPIO_BASE + 36), ///< P_GPIO_18
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PAD_PIN_PGPIO19 = (PAD_P_GPIO_BASE + 38), ///< P_GPIO_19
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PAD_PIN_PGPIO20 = (PAD_P_GPIO_BASE + 40), ///< P_GPIO_20
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PAD_PIN_PGPIO21 = (PAD_P_GPIO_BASE + 42), ///< P_GPIO_21
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PAD_PIN_PGPIO22 = (PAD_P_GPIO_BASE + 44), ///< P_GPIO_22
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PAD_PIN_PGPIO23 = (PAD_P_GPIO_BASE + 46), ///< P_GPIO_23
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PAD_PIN_PGPIO24 = (PAD_P_GPIO_BASE + 48), ///< P_GPIO_24
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//L_GPIO group
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PAD_PIN_LGPIO0 = (PAD_L_GPIO_BASE + 0), ///< L_GPIO_0
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PAD_PIN_LGPIO1 = (PAD_L_GPIO_BASE + 2), ///< L_GPIO_1
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PAD_PIN_LGPIO2 = (PAD_L_GPIO_BASE + 4), ///< L_GPIO_2
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PAD_PIN_LGPIO3 = (PAD_L_GPIO_BASE + 6), ///< L_GPIO_3
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PAD_PIN_LGPIO4 = (PAD_L_GPIO_BASE + 8), ///< L_GPIO_4
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PAD_PIN_LGPIO5 = (PAD_L_GPIO_BASE + 10), ///< L_GPIO_5
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PAD_PIN_LGPIO6 = (PAD_L_GPIO_BASE + 12), ///< L_GPIO_6
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PAD_PIN_LGPIO7 = (PAD_L_GPIO_BASE + 14), ///< L_GPIO_7
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PAD_PIN_LGPIO8 = (PAD_L_GPIO_BASE + 16), ///< L_GPIO_8
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PAD_PIN_LGPIO9 = (PAD_L_GPIO_BASE + 18), ///< L_GPIO_9 ///< Package not support
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//DSI_GPIO group
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PAD_PIN_DSIGPIO0 = (PAD_DSI_GPIO_BASE + 0), ///< DSI_GPIO_0
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PAD_PIN_DSIGPIO1 = (PAD_DSI_GPIO_BASE + 2), ///< DSI_GPIO_1
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PAD_PIN_DSIGPIO2 = (PAD_DSI_GPIO_BASE + 4), ///< DSI_GPIO_2
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PAD_PIN_DSIGPIO3 = (PAD_DSI_GPIO_BASE + 6), ///< DSI_GPIO_3
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PAD_PIN_DSIGPIO4 = (PAD_DSI_GPIO_BASE + 8), ///< DSI_GPIO_4
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PAD_PIN_DSIGPIO5 = (PAD_DSI_GPIO_BASE + 10), ///< DSI_GPIO_5
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PAD_PIN_DSIGPIO6 = (PAD_DSI_GPIO_BASE + 12), ///< DSI_GPIO_6
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PAD_PIN_DSIGPIO7 = (PAD_DSI_GPIO_BASE + 14), ///< DSI_GPIO_7
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PAD_PIN_DSIGPIO8 = (PAD_DSI_GPIO_BASE + 16), ///< DSI_GPIO_8
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PAD_PIN_DSIGPIO9 = (PAD_DSI_GPIO_BASE + 18), ///< DSI_GPIO_9
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PAD_PIN_DSIGPIO10 = (PAD_DSI_GPIO_BASE + 20), ///< DSI_GPIO_10
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//D_GPIO group
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PAD_PIN_DGPIO0 = (PAD_D_GPIO_BASE + 0), ///< D_GPIO_0 ///< Package not support
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PAD_PIN_DGPIO1 = (PAD_D_GPIO_BASE + 2), ///< D_GPIO_1 ///< Package not support
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PAD_PIN_DGPIO2 = (PAD_D_GPIO_BASE + 4), ///< D_GPIO_2
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PAD_PIN_DGPIO3 = (PAD_D_GPIO_BASE + 6), ///< D_GPIO_3
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PAD_PIN_DGPIO4 = (PAD_D_GPIO_BASE + 8), ///< D_GPIO_4
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PAD_PIN_DGPIO5 = (PAD_D_GPIO_BASE + 10), ///< D_GPIO_5
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PAD_PIN_DGPIO6 = (PAD_D_GPIO_BASE + 12), ///< D_GPIO_6
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PAD_PIN_DGPIO7 = (PAD_D_GPIO_BASE + 14), ///< D_GPIO_7
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PAD_PIN_DGPIO8 = (PAD_D_GPIO_BASE + 16), ///< D_GPIO_8 ///< Package not support
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PAD_PIN_DGPIO9 = (PAD_D_GPIO_BASE + 18), ///< D_GPIO_9 ///< Package not support
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PAD_PIN_DGPIO10 = (PAD_D_GPIO_BASE + 20), ///< D_GPIO_10 ///< Package not support
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//HSI_GPIO group
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PAD_PIN_HSIGPIO0 = (PAD_H_GPIO_BASE + 0), ///< HSI_GPIO_0
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PAD_PIN_HSIGPIO1 = (PAD_H_GPIO_BASE + 2), ///< HSI_GPIO_1
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PAD_PIN_HSIGPIO2 = (PAD_H_GPIO_BASE + 4), ///< HSI_GPIO_2
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PAD_PIN_HSIGPIO3 = (PAD_H_GPIO_BASE + 6), ///< HSI_GPIO_3
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PAD_PIN_HSIGPIO4 = (PAD_H_GPIO_BASE + 8), ///< HSI_GPIO_4
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PAD_PIN_HSIGPIO5 = (PAD_H_GPIO_BASE + 10), ///< HSI_GPIO_5
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PAD_PIN_HSIGPIO6 = (PAD_H_GPIO_BASE + 12), ///< HSI_GPIO_6
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PAD_PIN_HSIGPIO7 = (PAD_H_GPIO_BASE + 14), ///< HSI_GPIO_7
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PAD_PIN_HSIGPIO8 = (PAD_H_GPIO_BASE + 16), ///< HSI_GPIO_8
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PAD_PIN_HSIGPIO9 = (PAD_H_GPIO_BASE + 18), ///< HSI_GPIO_9
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PAD_PIN_HSIGPIO10 = (PAD_H_GPIO_BASE + 20), ///< HSI_GPIO_10
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PAD_PIN_HSIGPIO11 = (PAD_H_GPIO_BASE + 22), ///< HSI_GPIO_11
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//A_GPIO group
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PAD_PIN_AGPIO0 = (PAD_A_GPIO_BASE + 0), ///< A_GPIO_0
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PAD_PIN_AGPIO1 = (PAD_A_GPIO_BASE + 2), ///< A_GPIO_1
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PAD_PIN_AGPIO2 = (PAD_A_GPIO_BASE + 4), ///< A_GPIO_2
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PAD_PIN_MAX = PAD_PIN_AGPIO2,
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ENUM_DUMMY4WORD(PAD_PIN)
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} PAD_PIN;
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//@}
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/**
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Pad type select
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Pad type select
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Pad type value for pad_set_pull_updown(), pad_get_pull_updown().
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*/
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typedef enum {
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PAD_NONE = 0x00, ///< none of pull up/down
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PAD_PULLDOWN = 0x01, ///< pull down
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PAD_PULLUP = 0x02, ///< pull up
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PAD_KEEPER = 0x03, ///< keeper
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ENUM_DUMMY4WORD(PAD_PULL)
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} PAD_PULL;
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/**
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Pad driving select
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Pad driving select
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Pad driving value for pad_set_drivingsink(), pad_get_drivingsink().
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*/
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typedef enum {
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PAD_DRIVINGSINK_4MA = 0x0011, ///< Pad driver/sink 4mA
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PAD_DRIVINGSINK_10MA = 0x0002, ///< Pad driver/sink 10mA
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PAD_DRIVINGSINK_8MA = 0x0020, ///< Pad driver/sink 6mA
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PAD_DRIVINGSINK_12MA = 0x0840, ///< Pad driver/sink 16mA
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PAD_DRIVINGSINK_16MA = 0x0080, ///< Pad driver/sink 5mA
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PAD_DRIVINGSINK_3MA = 0x0100, ///< Pad driver/sink 15mA
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PAD_DRIVINGSINK_6MA = 0x0200, ///< Pad driver/sink 20mA
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PAD_DRIVINGSINK_9MA = 0x0400, ///< Pad driver/sink 25mA
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PAD_DRIVINGSINK_15MA = 0x1000, ///< Pad driver/sink 30mA
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PAD_DRIVINGSINK_18MA = 0x2000, ///< Pad driver/sink 35mA
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PAD_DRIVINGSINK_21MA = 0x4000, ///< Pad driver/sink 40mA
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PAD_DRIVINGSINK_24MA = 0x8000, ///< Pad driver/sink 8mA
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PAD_DRIVINGSINK_5MA = 0xf001, ///< not support
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PAD_DRIVINGSINK_20MA = 0xf002, ///< not support
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PAD_DRIVINGSINK_25MA = 0xf003, ///< not support
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PAD_DRIVINGSINK_30MA = 0xf004, ///< not support
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PAD_DRIVINGSINK_35MA = 0xf005, ///< not support
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PAD_DRIVINGSINK_40MA = 0xf006, ///< not support
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ENUM_DUMMY4WORD(PAD_DRIVINGSINK)
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} PAD_DRIVINGSINK;
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typedef enum {
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//C_GPIO group
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PAD_DS_CGPIO0 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< C_GPIO_0
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PAD_DS_CGPIO1 = ((PAD_C_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< C_GPIO_1
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PAD_DS_CGPIO2 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< C_GPIO_2
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PAD_DS_CGPIO3 = ((PAD_C_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< C_GPIO_3
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PAD_DS_CGPIO4 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< C_GPIO_4
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PAD_DS_CGPIO5 = ((PAD_C_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< C_GPIO_5
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PAD_DS_CGPIO6 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< C_GPIO_6
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PAD_DS_CGPIO7 = ((PAD_C_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< C_GPIO_7
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PAD_DS_CGPIO8 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< C_GPIO_8
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PAD_DS_CGPIO9 = ((PAD_C_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< C_GPIO_9
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PAD_DS_CGPIO10 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< C_GPIO_10
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PAD_DS_CGPIO11 = ((PAD_C_GPIO_BASE + 0) | PAD_DS_GROUP_40), ///< C_GPIO_11
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PAD_DS_CGPIO12 = ((PAD_C_GPIO_BASE + 4) | PAD_DS_GROUP_40), ///< C_GPIO_12
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PAD_DS_CGPIO13 = ((PAD_C_GPIO_BASE + 8) | PAD_DS_GROUP_40), ///< C_GPIO_13
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PAD_DS_CGPIO14 = ((PAD_C_GPIO_BASE + 12) | PAD_DS_GROUP_40), ///< C_GPIO_14
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PAD_DS_CGPIO15 = ((PAD_C_GPIO_BASE + 16) | PAD_DS_GROUP_40), ///< C_GPIO_15
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PAD_DS_CGPIO16 = ((PAD_C_GPIO_BASE + 20) | PAD_DS_GROUP_40), ///< C_GPIO_16
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PAD_DS_CGPIO17 = ((PAD_C_GPIO_BASE + 24) | PAD_DS_GROUP_40), ///< C_GPIO_17
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PAD_DS_CGPIO18 = ((PAD_C_GPIO_BASE + 36) | PAD_DS_GROUP_16), ///< C_GPIO_18
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PAD_DS_CGPIO19 = ((PAD_C_GPIO_BASE + 38) | PAD_DS_GROUP_16), ///< C_GPIO_19
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PAD_DS_CGPIO20 = ((PAD_C_GPIO_BASE + 40) | PAD_DS_GROUP_16), ///< C_GPIO_20
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PAD_DS_CGPIO21 = ((PAD_C_GPIO_BASE + 42) | PAD_DS_GROUP_16), ///< C_GPIO_21
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PAD_DS_CGPIO22 = ((PAD_C_GPIO_BASE + 44) | PAD_DS_GROUP_16), ///< C_GPIO_22
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//S_GPIO group
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PAD_DS_SGPIO0 = ((PAD_S_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< S_GPIO_0
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PAD_DS_SGPIO1 = ((PAD_S_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< S_GPIO_1
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PAD_DS_SGPIO2 = ((PAD_S_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< S_GPIO_2
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PAD_DS_SGPIO3 = ((PAD_S_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< S_GPIO_3
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PAD_DS_SGPIO4 = ((PAD_S_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< S_GPIO_4
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PAD_DS_SGPIO5 = ((PAD_S_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< S_GPIO_5
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PAD_DS_SGPIO6 = ((PAD_S_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< S_GPIO_6
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PAD_DS_SGPIO7 = ((PAD_S_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< S_GPIO_7
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PAD_DS_SGPIO8 = ((PAD_S_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< S_GPIO_8
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PAD_DS_SGPIO9 = ((PAD_S_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< S_GPIO_9 ///< Package not support
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PAD_DS_SGPIO10 = ((PAD_S_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< S_GPIO_10 ///< Package not support
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PAD_DS_SGPIO11 = ((PAD_S_GPIO_BASE + 22) | PAD_DS_GROUP_16), ///< S_GPIO_11 ///< Package not support
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PAD_DS_SGPIO12 = ((PAD_S_GPIO_BASE + 24) | PAD_DS_GROUP_16), ///< S_GPIO_12 ///< Package not support
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//P_GPIO group
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PAD_DS_PGPIO0 = ((PAD_P_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< P_GPIO_0
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PAD_DS_PGPIO1 = ((PAD_P_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< P_GPIO_1
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PAD_DS_PGPIO2 = ((PAD_P_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< P_GPIO_2
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PAD_DS_PGPIO3 = ((PAD_P_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< P_GPIO_3
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PAD_DS_PGPIO4 = ((PAD_P_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< P_GPIO_4
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PAD_DS_PGPIO5 = ((PAD_P_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< P_GPIO_5
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PAD_DS_PGPIO6 = ((PAD_P_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< P_GPIO_6
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PAD_DS_PGPIO7 = ((PAD_P_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< P_GPIO_7
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PAD_DS_PGPIO8 = ((PAD_P_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< P_GPIO_8
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PAD_DS_PGPIO9 = ((PAD_P_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< P_GPIO_9
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PAD_DS_PGPIO10 = ((PAD_P_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< P_GPIO_10
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PAD_DS_PGPIO11 = ((PAD_P_GPIO_BASE + 22) | PAD_DS_GROUP_16), ///< P_GPIO_11
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PAD_DS_PGPIO12 = ((PAD_P_GPIO_BASE + 24) | PAD_DS_GROUP_16), ///< P_GPIO_12
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PAD_DS_PGPIO13 = ((PAD_P_GPIO_BASE + 26) | PAD_DS_GROUP_16), ///< P_GPIO_13 ///< Package not support
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PAD_DS_PGPIO14 = ((PAD_P_GPIO_BASE + 28) | PAD_DS_GROUP_16), ///< P_GPIO_14 ///< Package not support
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PAD_DS_PGPIO15 = ((PAD_P_GPIO_BASE + 30) | PAD_DS_GROUP_16), ///< P_GPIO_15 ///< Package not support
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PAD_DS_PGPIO16 = ((PAD_P_GPIO_BASE + 32) | PAD_DS_GROUP_16), ///< P_GPIO_16 ///< Package not support
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PAD_DS_PGPIO17 = ((PAD_P_GPIO_BASE + 34) | PAD_DS_GROUP_16), ///< P_GPIO_17
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PAD_DS_PGPIO18 = ((PAD_P_GPIO_BASE + 36) | PAD_DS_GROUP_16), ///< P_GPIO_18
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PAD_DS_PGPIO19 = ((PAD_P_GPIO_BASE + 38) | PAD_DS_GROUP_16), ///< P_GPIO_19
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PAD_DS_PGPIO20 = ((PAD_P_GPIO_BASE + 40) | PAD_DS_GROUP_16), ///< P_GPIO_20
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PAD_DS_PGPIO21 = ((PAD_P_GPIO_BASE + 42) | PAD_DS_GROUP_16), ///< P_GPIO_21
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PAD_DS_PGPIO22 = ((PAD_P_GPIO_BASE + 44) | PAD_DS_GROUP_16), ///< P_GPIO_22
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PAD_DS_PGPIO23 = ((PAD_P_GPIO_BASE + 46) | PAD_DS_GROUP_16), ///< P_GPIO_23
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PAD_DS_PGPIO24 = ((PAD_P_GPIO_BASE + 48) | PAD_DS_GROUP_16), ///< P_GPIO_24
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//L_GPIO group
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PAD_DS_LGPIO0 = ((PAD_L_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< L_GPIO_0
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PAD_DS_LGPIO1 = ((PAD_L_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< L_GPIO_1
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PAD_DS_LGPIO2 = ((PAD_L_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< L_GPIO_2
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PAD_DS_LGPIO3 = ((PAD_L_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< L_GPIO_3
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PAD_DS_LGPIO4 = ((PAD_L_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< L_GPIO_4
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PAD_DS_LGPIO5 = ((PAD_L_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< L_GPIO_5
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PAD_DS_LGPIO6 = ((PAD_L_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< L_GPIO_6
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PAD_DS_LGPIO7 = ((PAD_L_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< L_GPIO_7
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PAD_DS_LGPIO8 = ((PAD_L_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< L_GPIO_8
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PAD_DS_LGPIO9 = ((PAD_L_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< L_GPIO_9 ///< Package not support
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//D_GPIO group
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PAD_DS_DGPIO0 = ((PAD_D_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< D_GPIO_0 ///< Package not support
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PAD_DS_DGPIO1 = ((PAD_D_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< D_GPIO_1 ///< Package not support
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PAD_DS_DGPIO2 = ((PAD_D_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< D_GPIO_2
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PAD_DS_DGPIO3 = ((PAD_D_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< D_GPIO_3
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PAD_DS_DGPIO4 = ((PAD_D_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< D_GPIO_4
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PAD_DS_DGPIO5 = ((PAD_D_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< D_GPIO_5
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PAD_DS_DGPIO6 = ((PAD_D_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< D_GPIO_6
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PAD_DS_DGPIO7 = ((PAD_D_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< D_GPIO_7
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PAD_DS_DGPIO8 = ((PAD_D_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< D_GPIO_8 ///< Package not support
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PAD_DS_DGPIO9 = ((PAD_D_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< D_GPIO_9 ///< Package not support
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PAD_DS_DGPIO10 = ((PAD_D_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< D_GPIO_10 ///< Package not support
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//HSI_GPIO group
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PAD_DS_HSIGPIO0 = ((PAD_H_GPIO_BASE + 0) | PAD_DS_GROUP_10), ///< HSI_GPIO_0
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PAD_DS_HSIGPIO1 = ((PAD_H_GPIO_BASE + 2) | PAD_DS_GROUP_10), ///< HSI_GPIO_1
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PAD_DS_HSIGPIO2 = ((PAD_H_GPIO_BASE + 4) | PAD_DS_GROUP_10), ///< HSI_GPIO_2
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PAD_DS_HSIGPIO3 = ((PAD_H_GPIO_BASE + 6) | PAD_DS_GROUP_10), ///< HSI_GPIO_3
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PAD_DS_HSIGPIO4 = ((PAD_H_GPIO_BASE + 8) | PAD_DS_GROUP_10), ///< HSI_GPIO_4
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PAD_DS_HSIGPIO5 = ((PAD_H_GPIO_BASE + 10) | PAD_DS_GROUP_10), ///< HSI_GPIO_5
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PAD_DS_HSIGPIO6 = ((PAD_H_GPIO_BASE + 12) | PAD_DS_GROUP_10), ///< HSI_GPIO_6
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PAD_DS_HSIGPIO7 = ((PAD_H_GPIO_BASE + 14) | PAD_DS_GROUP_10), ///< HSI_GPIO_7
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PAD_DS_HSIGPIO8 = ((PAD_H_GPIO_BASE + 16) | PAD_DS_GROUP_10), ///< HSI_GPIO_8
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PAD_DS_HSIGPIO9 = ((PAD_H_GPIO_BASE + 18) | PAD_DS_GROUP_10), ///< HSI_GPIO_9
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PAD_DS_HSIGPIO10 = ((PAD_H_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< HSI_GPIO_10
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PAD_DS_HSIGPIO11 = ((PAD_H_GPIO_BASE + 22) | PAD_DS_GROUP_16), ///< HSI_GPIO_11
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//A_GPIO group
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PAD_DS_AGPIO0 = ((PAD_A_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< A_GPIO_0
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PAD_DS_AGPIO1 = ((PAD_A_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< A_GPIO_1
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PAD_DS_AGPIO2 = ((PAD_A_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< A_GPIO_2
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//DSI_GPIO group
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PAD_DS_DSIGPIO0 = ((PAD_DS_DSI_GPIO_BASE + 0) | PAD_DS_GROUP_16), ///< DSI_GPIO_0
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PAD_DS_DSIGPIO1 = ((PAD_DS_DSI_GPIO_BASE + 2) | PAD_DS_GROUP_16), ///< DSI_GPIO_1
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PAD_DS_DSIGPIO2 = ((PAD_DS_DSI_GPIO_BASE + 4) | PAD_DS_GROUP_16), ///< DSI_GPIO_2
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PAD_DS_DSIGPIO3 = ((PAD_DS_DSI_GPIO_BASE + 6) | PAD_DS_GROUP_16), ///< DSI_GPIO_3
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PAD_DS_DSIGPIO4 = ((PAD_DS_DSI_GPIO_BASE + 8) | PAD_DS_GROUP_16), ///< DSI_GPIO_4
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PAD_DS_DSIGPIO5 = ((PAD_DS_DSI_GPIO_BASE + 10) | PAD_DS_GROUP_16), ///< DSI_GPIO_5
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PAD_DS_DSIGPIO6 = ((PAD_DS_DSI_GPIO_BASE + 12) | PAD_DS_GROUP_16), ///< DSI_GPIO_6
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PAD_DS_DSIGPIO7 = ((PAD_DS_DSI_GPIO_BASE + 14) | PAD_DS_GROUP_16), ///< DSI_GPIO_7
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PAD_DS_DSIGPIO8 = ((PAD_DS_DSI_GPIO_BASE + 16) | PAD_DS_GROUP_16), ///< DSI_GPIO_8
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PAD_DS_DSIGPIO9 = ((PAD_DS_DSI_GPIO_BASE + 18) | PAD_DS_GROUP_16), ///< DSI_GPIO_9
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PAD_DS_DSIGPIO10 = ((PAD_DS_DSI_GPIO_BASE + 20) | PAD_DS_GROUP_16), ///< DSI_GPIO_10
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PAD_DS_MAX = PAD_DS_DSIGPIO10,
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ENUM_DUMMY4WORD(PAD_DS)
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} PAD_DS;
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/**
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Pad power ID select
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Pad power ID for PAD_POWER_STRUCT.
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*/
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typedef enum {
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PAD_POWERID_MC0 = 0x00, ///< Pad power id for MC0
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PAD_POWERID_MC1 = 0x01, ///< Pad power id for MC1
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PAD_POWERID_ADC = 0x02, ///< Pad power id for ADC
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PAD_POWERID_CSI = 0x04, ///< Pad power id for CSI
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ENUM_DUMMY4WORD(PAD_POWERID)
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} PAD_POWERID;
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/**
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Pad power select
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Pad power value for PAD_POWER_STRUCT.
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*/
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typedef enum {
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PAD_3P3V = 0x00, ///< Pad power is 3.3V
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PAD_AVDD = 0x00, ///< Pad power is AVDD ( for PAD_POWERID_ADC use)
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PAD_1P8V = 0x01, ///< Pad power is 1.8V
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PAD_PAD_VAD = 0x01, ///< Pad power is PAD_ADC_VAD ( for PAD_POWERID_ADC use)
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ENUM_DUMMY4WORD(PAD_POWER)
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} PAD_POWER;
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/**
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Pad power VAD for PAD_POWERID_ADC
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Pad power VAD value for PAD_POWER_STRUCT.
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*/
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typedef enum {
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PAD_VAD_2P9V = 0x00, ///< Pad power VAD = 2.9V <ADC>
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PAD_VAD_3P0V = 0x01, ///< Pad power VAD = 3.0V <ADC>
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PAD_VAD_3P1V = 0x03, ///< Pad power VAD = 3.1V <ADC>
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PAD_VAD_2P4V = 0x100, ///< Pad power VAD = 2.4V <CSI>
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PAD_VAD_2P5V = 0x101, ///< Pad power VAD = 2.5V <CSI>
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PAD_VAD_2P6V = 0x103, ///< Pad power VAD = 2.6V <CSI>
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ENUM_DUMMY4WORD(PAD_VAD)
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} PAD_VAD;
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/**
|
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PAD power structure
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|
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PAD power setting for pad_setPower()
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*/
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typedef struct {
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PAD_POWERID pad_power_id; ///< Pad power id
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PAD_POWER pad_power; ///< Pad power
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BOOL bias_current; ///< Regulator bias current selection
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///< - @b FALSE: disable
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///< - @b TRUE: enable
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BOOL opa_gain; ///< Regulator OPA gain/phase selection
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///< - @b FALSE: disable
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///< - @b TRUE: enable
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BOOL pull_down; ///< Regulator output pull down control
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///< - @b FALSE: none
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///< - @b TRUE: pull down enable
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BOOL enable; ///< Regulator enable
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///< - @b FALSE: disable
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///< - @b TRUE: enable
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PAD_VAD pad_vad; ///< Pad VAD of PAD_POWERID_ADC when PAD_PAD_VAD = 1
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} PAD_POWER_STRUCT;
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extern ER pad_set_pull_updown(PAD_PIN pin, PAD_PULL pulltype);
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extern ER pad_get_pull_updown(PAD_PIN pin, PAD_PULL *pulltype);
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extern ER pad_set_drivingsink(PAD_DS name, PAD_DRIVINGSINK driving);
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extern ER pad_get_drivingsink(PAD_DS name, PAD_DRIVINGSINK *driving);
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extern ER pad_set_power(PAD_POWER_STRUCT *pad_power);
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extern void pad_get_power(PAD_POWER_STRUCT *pad_power);
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//@}
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#endif
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